SMR101

Preliminary Information

(See Last Page)

© SUMMIT Microelectronics, Inc.

2004 ·

1717 Fox Drive · San Jose CA 95131 ·

Phone 408 436-9890 · FAX 408 436-9897

http://www.summitmicro.com

209

1 2.1 4/21/2005

· Two Programmable Reset Outputs, SOFT_RST#

And HARD_RST#

· De-Bounced Push-Button Reset Input With a

Programmable Delay Up To 40 Seconds Prior To
Reset Assertion

· 8 Programmable Settings For Both SOFT_RST#

And HARD_RST# Delay

· Programmable Voltage Monitor With 8 Voltage

Settings To Trigger SOFT_RST# Output

· Programmable Reset Output Duration From 1-

200ms

· Built-In 15us Voltage Glitch Filtering And Input

"De-Bouncing"

· 6 Ball Ultra CSP

(Chip-Scale) Package

· 8 Lead SOIC Package

Applications

· PDAs, Handheld PCs, Cameras, Camcorders
· Handheld GPS Equipment
· Satellite And Cable-TV Set-Top Box

The SMR101 is a programmable reset controller
especially designed for embedded consumer
electronics. The device provides dual outputs that can
be used to implement "soft" and "hard" system resets.
Both resets can be triggered by an external reset input,
and an internal voltage monitor can trigger the soft
reset. Typically a "soft" reset applies to volatile registers
in an embedded controller while a hard reset is
equivalent to a full power cycle without the associated
power-up delays. The SMR101 receives an external
push-button input using an internal programmable de-
bounced timer. The push button input hold down time is
programmable up to 40 seconds with an internal on-chip
timer. A "short" hold down time (0.125-10 sec) asserts
the SOFT_RST# pin while a long hold down time (0.5-
40 sec) asserts the HARD_RST# pin. Both reset
outputs have programmable output durations from 1-
200ms. Additionally, voltage monitoring is provided via a
programmable threshold detector (2.30V 4.50V) on
the VDD pin. This voltage detector asserts the
SOFT_RST# pin for the same 1-200ms output duration
as above. A 15us glitch filter avoids nuisance tripping
that can result in unnecessary system resets. The
SMR101 is factory programmed, to default values;
however, multiplexed programming pins are also
provided for in-system programming for prototype
purposes.

FILT_CAP

TRIM_C

SMR101

3.3V

2.7V

5.5V

RESET_IN#

HARD_RST#

SOFT_RST#

0.1

µf

µP

Manual

Reset

Switch

Figure 1 Applications schematic using the SMR101 to supervise an embedded controller. As shown, the
SMR101 implements a two-level RESET function including external manual input.

SIMPLIFIED APPLICATIONS DRAWING

FEATURES & APPLICATIONS

INTRODUCTION

SMR101

Preliminary Information

Summit Microelectronics, Inc 209

1 2.1 4/21/2005

Figure 2 SMR101 Operation and timing diagram.

The SMR101 is a programmable reset controller that
monitors the power supply in µP and digital systems
for under voltage conditions The integrated feature set
provides excellent circuit reliability and low cost by
eliminating external components while the
programmable settings allow "on the fly" adjustments
necessary for modern control techniques.
The device performs several functions: it first asserts a
"soft" reset signal whenever the VDD supply voltage
declines below a preset threshold, keeping it asserted
for a programmable time period after VDD has risen
above the reset threshold. The part also provides a
push button input with two programmable delays for
hierarchical manual system reset.
The open-drain SOFT_RST# and HARD_RST#
outputs have on-chip 100K pull-up resistors and do not
require external pull-up resistors unless more drive
current is needed (see figure 3). The SOFT_RST#
comparator is designed to ignore fast transients on
VDD, and the output is guaranteed to be in the correct
logic state for VDD down to 1V. Low supply current
makes the SMR101 ideal for use in portable
equipment. The RESET_IN# input includes a
programmable hold-down delay timer for use with a
push button switch for consumer equipment such as
set-top boxes and PCs.
A microprocessor's (µP's) reset input starts the µP in a
known state. The SMR101 asserts a SOFT_RST# to

prevent code execution errors during power-up,
power-down, or UnderVoltage (UV) conditions
whenever the VDD supply voltage declines below a
programmed limit (V

MON

). There are 8 programmable

voltage settings to trigger the SOFT_RST# output.
SOFT_RST# stays asserted for a programmable
period after VDD has risen above the reset threshold.
The SOFT_RST# signal is also asserted whenever the
RESET_IN# input is asserted for a programmed delay.
There are 8 programmable timing settings (T

RESET_SR

)

to trigger SOFT_RST# output. The HARD_RST#
signal is also asserted whenever the RESET_IN#
input is asserted for a separate programmed delay.
There are 8 programmable timing settings (T

RESET_HR

)

to trigger the HARD_RST# output. It is recommended
that the soft reset time be of a shorter duration than
that of the HARD_RST#.
In addition to issuing a reset to the µP during power-
up, power-down, and brownout conditions, the
SMR101 is immune to short-duration VDD transients
(glitches) due to an internal glitch filter. A external
0.1µF bypass capacitor mounted as close as possible
to the VDD pin provides additional transient immunity.
Since the SOFT_RST# and HARD_RST# outputs are
open drain, the device interfaces easily with µPs that
have bidirectional-reset pins. Connecting the
SOFT_RST# output directly to the µP's RESET pin
allows either the µP or the SMR101 to assert a reset.

GENERAL DESCRIPTION

VDD

HARD_RST#

SOFT_RST#

RESET_IN#

Push-Button

Input

RESET

RESET_HR

RESET

VMON

GLITCH

Push-Button

Released

RESET

Push-Button

Engaged

Push-Button

Engaged

Push-Button

Released

RESET

RESET_SR

SMR101

Preliminary Information

Summit Microelectronics, Inc 209

1 2.1 4/21/2005

8 KHz

Ring

Oscillator,

+/-10%

accurate

Programmable Delay Generator/

Logic

Up Count

MSB

Programmable

Hold-Down Time,

0.125 to 40 Sec

VDD

GND

User Reset

Pushbutton

Vref

Glitch Filter

Reset Input

RESET _IN#

HARD_RST#

SOFT_RST#

2.7V_5.5V

SOFT_RST at

2.30V-4.5V

100k

PROG

r
ogrammable

Dura

tion Res

e
t

utput

Figure 3 SMR101 Internal Block Diagram.

Pushbutton Input delay (seconds)

Voltage Monitor Threshold (V)

RESET Timeout Period (ms)

Register

Value

HARD_RST# Register

Value

SOFT_RST#

Register Value

Voltage

Register Value

Time

000 0.5 000

0.125 000

4.50

001 1 001

0.25 001 4.25

010 2 010 0.5 010 2.97

100

011 4 011 1 011 2.81

200

100 8 100 2 100 2.70

101 16 101 4 101

2.55

110 32 110 8 110

2.43

111 40 111 10 111

2.30

Figure 4 SMR101 Register Maps. The SMR101 is user programmable using the SMX3199 Programmer and the
SMR101 Windows GUI.

INTERNAL BLOCK DIAGRAM

SMR101

Preliminary Information

Summit Microelectronics, Inc 209

1 2.1 4/21/2005

PIN DESCRIPTIONS

PACKAGE AND PIN CONFIGURATION

RESET_IN#

VDD

HARD_RST#

GND

PROG

A1 A2

C1 C2

SOFT_RST#

PROG

RESET_IN#

GND

VDD

SOFT_RST#

HARD_RST#

CSP

Ball

Number

SOIC

Lead

Number

Pin

Type

Pin Name

Pin Description

1 I

PROG

High voltage programming pin. Connected to ground during
normal operation.

8 PWR

VDD

Positive supply voltage.

4 PWR

GND

Ground pin.

5 O

HARD_RST#

Open Drain active low Hard Reset Out indicator. Internally
connected to VDD through a 100K

resistor.

3 I

RESET_IN#

De-bounced push button switch input. Internally connected to VDD
through a 100K

resistor. Also used as the Data input

programming pin.

6 O

SOFT_RST#

Open Drain active low Soft Reset Out indicator. Internally
connected to VDD through a 100K

resistor.

2,7 NC

No Connect

6 Ball Ultra CSP

Bottom View

8 Lead SOIC

Top View

PACKAGE AND PIN CONFIGURATION

SMR101

Preliminary Information

Summit Microelectronics, Inc 209

1 2.1 4/21/2005

Temperature Under Bias .......................-55

C to +125

Storage Temperature.............................-65

C to +125

Terminal Voltage with Respect to GND:

........................................-0.3V to +6.0V

PROG,

RESET_IN#.................... -0.3V to +16.0V

All

Others .......................................... VDD + 0.7V

Output

Short

Circuit Current .....................100mA

Reflow Solder Temperature (30 secs)....................260

ESD Rating per JEDEC....................................2000V
Latch-Up testing per JEDEC............ ... ............±100mA

Note - The device is not guaranteed to function outside its operating
rating. Stresses listed under Absolute Maximum Ratings may cause
permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions
outside those listed in the operational sections of the specification is
not implied. Exposure to any absolute maximum rating for extended
periods may affect device performance and reliability. Devices are
ESD sensitive. Handling precautions are recommended.

Temperature Range (Commercial). ..........0

C to +70

Supply Voltage

......................................3.3V +/-10%

Note 1 The device can operate over a supply range of
2.7V to 5.5V.

Package Thermal Resistance (

)

8 Lead SOIC.................................................23

C/W

6 Ball Ultra CSP

........................................TBD

C/W

Moisture Classification Level 1 (MSL 1) per J-STD- 020

RELIABILITY CHARACTERISTICS
Data Retention ...........................................100 Years
Endurance.........................................100,000 Cycles

(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.)

Symbol Parameter

Notes

Min.

Typ.

Max

Unit

Supply Voltage Range

2.7

3.3

5.5

VDD = 3.3V, no
RESET in progress.

Power Supply Current

VDD = 5.5V, no
RESET in progress.

µA

GLITCH

Glitch filter time

µs

Input High Voltage

VDD = 3.3V 0.9xVDD

VDD

Input Low Voltage

VDD = 3.3V

0.1xVDD

Open Drain Outputs (HARD_RST#,
SOFT_RST#)

ISINK = 1mA

0.4

Output Low Current

0 1.0

DC OPERATING CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATION CONDITIONS

SMR101

Preliminary Information

Summit Microelectronics, Inc 209

1 2.1 4/21/2005

(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.)

Symbol Parameter

Notes

Min.

Typ.

Max

Unit

0.80 1

1.20

20 25 30

80 100 120

RESET

Reset Output Timeout period

Programmed Default = 100ms

160 200 240

4.41 4.5

4.59

4.16 4.25 4.34

2.91 2.97 3.03

2.75 2.81 2.87

2.64 2.7

2.76

2.5 2.55 2.6

2.38 2.43 2.48

MON

Voltage Monitor Threshold

Programmed Default = 2.97V

2.25 2.3

2.35

0.10 0.125 0.15

0.20 0.25 0.30

0.40 0.5

0.60

0.80 1

1.20

1.60 2

2.40

3.20 4

4.80

6.40 8

9.60

RESET_SR

Programmable Reset Hold-
Down Delay times (soft reset)

Programmed Default = 0.25s

8 10 12

0.40 0.5

0.60

0.80 1

1.20

1.60 2

2.40

3.20 4

4.80

6.40 8

9.60

12.80 16

19.20

25.60 32

38.40

RESET_HR

Programmable Reset Hold-
Down Delay times (hard reset)

Programmed Default = 4s

32 40 48

Note 1 - Voltage monitor threshold accuracies are relative to factory programmed setting, deviation from this setting can
result in errors exceeding those stated above.

AC OPERATING CHARACTERISTICS

SMR101

Preliminary Information

Summit Microelectronics, Inc 209

1 2.1 4/21/2005

SUMMIT

SMR101S

AYYWW

Pin 1

Annn

Summit
Part Number

Date Code (YYWW)

Part Number suffix
(Contains Customer specific
ordering requirements)

Lot tracking code (Summit use)

Drawing not

to scale

Status Tracking Code
(01, 02,...)
(Summit Use)

Product Tracking Code (Summit use)

SMR101

Package

E = 6 Ball Ultra CSP

Summit Part Number

nnn

Part Number Suffix

Customer specific requirements are contained
in the suffix such as Hex code, Hex code
revision, etc.

S = 8 Lead SOIC

The default device ordering number is SMR101E-316 and is programmed as described in the AC Operating
Characteristics table on page 6 and tested over the commercial temperature range.

NOTICE

NOTE 1 - This is a Preliminary Information data sheet that describes a Summit product currently in pre-production with limited
characterization.

SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve
design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described
herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent
infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a
user's specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc.
shall not be liable for any damages arising as a result of any error or omission.
SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the
failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their
safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives
written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such
risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances.

Device Errata sheets can be accessed at:

http://www.summitmicro.com/errata/

Revision 2.1 - This document supersedes all previous versions. Please check the Summit Microelectronics Inc. web site at

http://www.summitmicro.com

for data sheet updates.

5 SUMMIT MICROELECTRONICS, Inc. PROGRAMMABLE ANALOG FOR A DIGITAL WORLDTM

Ultra CSP

is a registered name of FlipChip International, LLC.

6 Ball Ultra CSP

8 Lead SOIC

PART MARKING

An
nn

SSYWW

Ball A1

Identifier

Part Number suffix
(Customer specific
ordering requirements)

Date Code
Y = Single digit year
(4=2004, 5=2005, etc)

Drawing not

to scale

Product Tracking Code
(Summit use)

ORDERING INFORMATION

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SMR101E

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SMR101E