1
HV301/HV311
08/26/02
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
Features
10V to 90V Operation
Built-in "normally on" turn-on clamp eliminates components
UV/OV Lock Out & Power-on-Reset(POR) for Debouncing
Sense resistor programmed circuit breaker
Programmable circuit breaker holdoff
Inrush control using either: i) servo or ii) feedback cap
Feedback to Ramp pin means no Gate Clamp needed
Application solution for input voltage step (diode "ORing")
Programmable Auto-Retry (tens of seconds if desired)
Auto-Retry or Latched Operation
Enable through Open Drain interface to UV or OV
Low Power, <0.6mA , <0.4mA Sleep Mode
PWRGD Flag
Small SOIC-8 Package
Applications
-48V Central Office Switching
-24V Cellular and Fixed Wireless Systems
-24V PBX Systems
Line Cards
-48V Powered Ethernet for VoIP
Distributed Power Systems
Power Supply Control
+48V Storage Networks
Electronic Circuit Breaker
General Description
The Supertex HV301 and HV311 Hotswap Controllers provide
control of power supply connection during insertion of cards or
modules into live backplanes. They may be used in systems
where active control is implemented in the negative lead of
supplies ranging from 10V to 90V.
During initial power application the gate of the external pass
device is clamped low to suppress contact bounce glitches by a
"normally on" circuit which does not require initialization of the
IC. Thereafter the UV/OV supervisors and power-on-reset work
together to suppress gate turn on until mechanical bounce has
ended. The HV301/311 then control the current inrush limit to a
programmed level using one of two possible methods, i) servo
control or ii) a drain to ramp capacitor. The above methods
eliminate the need for extra hold-off or current limiting compo-
nents. The devices also include an electronic circuit breaker,
programmed by a sense resistor.
After the load capacitance has fully charged, the HV301/311 will
transition into a low power mode, and enable the open drain
PWRGD. In low power mode the HV301/311 continues to moni-
tor the input voltage and monitor the current level. If a load fault
occurs, the electronic circuit breaker will trip, the pass
element will be turned off, and the PWRGD will return to an
(continued on Page 21)
VDD
UV
OV
VEE
SENSE
GATE
-48V
R4
12.5m
R1
487k
R2
6.81k
R3
9.76k
Q1
IRF530
Cload
+5V
HV301/
HV311
8
3
2
5
4
COM
DC/DC
PWM
CONVERTER
1
GND
PWRGD / PWRGD
ENABLE / ENABLE
6
RAMP
7
C1
10nF
C2
-48V
Notes: 1. Undervoltage Shutdown (UV) set to 35V.
2. Overvoltage Shutdown (OV) set to 65V.
3. Current Limit set to -1A.
4. CB set to 8A.
Typical Application Circuit
0.75nF
Hotswap, Controllers with Circuit Breaker
(Negative Supply Rail)
HV301
HV311
Demo Kit
Available
2
HV301/HV311
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Electrical Characteristics
(-10V V
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-90V, -40C +85C unless otherwise noted)
Note 1: This timing depends on the threshold voltage of the external N-Channel MOSFET. The higher its threshold is, the longer this timing.
Note 2: This voltage depends on the characteristics of the external N-Channel MOSFET. V
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= 3V for an IRF530.
* IRF530 is a registered trademark of International Rectifier.
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HV301/HV311
Absolute Maximum Ratings
V
EE
reference to V
DD
pin
+0.3V to -100V
V
PWRGD
referenced to V
EE
Voltage
-0.3V to +100V
V
UV
and V
OV
referenced to V
EE
Voltage
-0.3V to +12V
Operating Ambient Temperature
-40C to +85C
Operating Junction Temperature
-40C to +125C
Storage Temperature Range
-65C to +150C
Pin Description
PWRGD The Power Good Output Pin is held inactive on initial
power application and will go active when the external MOSFET
is fully turned on. This pin may be used as an enable control
when connected directly to a PWM power module.
OV This OverVoltage (OV) sense pin, when raised above its
high threshold will immediately cause the GATE pin to be pulled
low. The GATE pin will remain low until the voltage on this pin falls
below the low threshold limit, initiating a new start-up cycle.
UV This UnderVoltage (UV) sense pin, when below its low
threshold limit will immediately cause the GATE pin to be pulled
low. The GATE pin will remain low until the voltage on this pin
rises above the high threshold limit, initiating a new start-up
cycle.
V
EE
This pin is the negative terminal of the power supply input
to the circuit.
V
DD
This pin is the positive terminal of the power supply input
to the circuit.
RAMP This pin provides a current output so that a timing ramp
voltage is generated when a capacitor is connected.
GATE This is the Gate Driver Output for the external N-
Channel MOSFET.
SENSE The current sense resistor connected from this pin to
V
EE
Pin programs the circuit breaker trip limit.
General Description, cont'd.
PWRGD Logic
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inactive state. Thereafter a programmable auto-retry timer will
hold the device off to allow the pass element to cool before
resetting and restarting. The auto-retry can be disabled using a
single resistor if desired.
The HV301/HV311 includes a current mode servo-circuit which
can be used as a return to limit during input voltage steps such
as would be seen in a diode "ORed" situation when power
switches back to regulated supply from battery operation. The
HV301/HV311 allow independent programming of the trigger
level of this phenomenon so that it may be set at a different level
to the current limit level if desired. Under all circumstances the
maximum servo period is limited to 100ms to protect the pass
element.
Pinout
PWRGD (HV301)
PWRGD (HV311)
OV
UV
V
EE
VDD
RAMP
GATE
SENSE
1
2
3
4
8
7
6
5
Ordering Information
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V
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5.00ms/div
Waveforms
Drain
50V/div
V
IN
50V/div
Gate
5.00V/div
I
inrush
500mA/div
4
HV301/HV311
Functional Block Diagram
Functional Description
Insertion into Hot Backplanes
Telecom, data networks and some computer applications re-
quire the ability to insert and remove circuit cards from systems
without powering down the entire system. All circuit cards have
some filter capacitance on the power rails, which is especially
true in circuit cards or network terminal equipment utilizing
distributed power systems. The insertion can result in high inrush
currents that can cause damage to connector and circuit cards
and may result in unacceptable disturbances on the system
backplane power rails.
The HV301 and HV311 are designed to facilitate the insertion of
these circuit cards or connection of terminal equipment by
eliminating these inrush currents and powering up these circuits
in a controlled manner after full connector insertion has been
achieved. The HV301 or HV311 is intended to provide this
function on supply rails in the range of 10 to 90 Volts.
Description of Operation
During initial power application, a unique proprietary circuit holds
off the external MOSFET, preventing an input glitch while an
internal regulator establishes an internal operating voltage of
approximately 10V. Until the proper internal voltage is achieved
all circuits are held reset, the PWRGD output is inactive and the
gate to source voltage of the external MOSFET is clamped low.
Once the internal under voltage lock out (UVLO) has been
satisfied, the circuit checks the input supply undervoltage (UV)
and overvoltage (OV) sense circuits to ensure that the input
voltage is within programmed limits. These limits are determined
by the selected values of resistors R1, R2 and R3, which form a
voltage divider.
Assuming the above conditions are satisfied and while continu-
ing to hold the PWRGD output inactive and the external MOSFET
GATE voltage low, the current source feeding the RAMP pin is
turned on. The external capacitor connected to it begins to
charge, thus starting an initial time delay determined by the value
of the capacitor. During this time if the OV or UV limits are
exceeded, an immediate reset occurs and the capacitor con-
nected to the RAMP pin is discharged.
When the voltage on the RAMP pin reaches an internally set
threshold voltage, the gate drive circuit begins to turn on the
external MOSFET. In servo mode, once the gate threshold is
reached, the resulting output current generates a voltage drop
on the sense resistor connected between the SENSE and V
EE
pins, causing a decrease in the available current charging the
capacitor on the RAMP pin. This continuous feedback mecha-
nism allows the output current to rise inverse exponentially over
a period of a few hundred microseconds to the sense resistor
programmed current limit set point.
When the voltage drop on the sense resistor reaches 50mV the
RAMP pin current is reduced to zero and the voltage on the
Vbg
C
C
C
UV
OV
Logic
Regulator & POR
V
IN
PWRGD = HV301
PWRGD = HV311
~9.8V
RAMP
2V
bg
gm
SENSE
10
A
Transconductor
D
I
S
A
B
L
E
P
U
L
L
H
I
G
H
V
DD
1 : 2
buffer
mirror
GATE
5k
5k
Latch High
Sleep
Clamp Mechanism
Transconductor
UVLO
V
EE
5
HV301/HV311
RAMP pin will be fixed, indicating that the circuit is in current limit
mode. Depending on the value of the load capacitor and the
programmed current limit, charging may continue for some time,
but may not exceed a nominal 100ms preset time limit. Once the
load capacitor has been charged, the output current will drop,
reducing the voltage on the SENSE pin, which in turn will
increase the RAMP pin current, thus causing the voltage on the
capacitor connected to the RAMP pin to continue rising, thereby
providing yet another programmed delay. If due to output over-
load conditions during startup, PWRGD does not achieve an
active state within 100ms or the circuit breaker is tripped, the
circuit is reset, pulling down the GATE to V
EE
, discharging the
capacitor connected to the RAMP pin, changing PWRGD to an
inactive state. A timeout or circuit breaker fault will initiate an
auto-retry if enabled.
On the other hand, in feedback capacitor mode, a current source
of 10A from the RAMP pin limits the dv/dt of the feedback
capacitor which, in turn, programs Inrush according to
Inrush ~ 10AC
load
/C
2
. (See Programming Inrush and I
CB
for
accurate formula on page 6.)
When the ramp voltage is within 1.2V of the regulated internal
supply voltage, the controller will force the GATE terminal to a
nominal 10V, the PWRGD pin will change to an active state, the
circuit breaker supervisor is enabled and the circuit will transition
to a low power sleep mode.
When the voltage on the SENSE pin rises to 100mV, indicating
an over current condition, the circuit breaker will trip in less than
5s. This time may be extended by the addition of external
components.
At any time during the start up cycle or thereafter, crossing the
UV and OV limits (including hysteresis) will cause an immediate
reset of all internal circuitry. When the input supply voltage
returns to a value within the programmed UV and OV limits a new
start up sequence will be initiated.
Functional Description, cont'd.
Design Information
Setting UnderVoltage and OverVoltage Shut Down
The UV and OV pins are connected to comparators with nominal
1.21V thresholds and 100mV of hysteresis (1.21V 50mV).
They are used to detect under voltage and over voltage condi-
tions at the input to the circuit. Whenever the OV pin rises above
its high threshold (1.26V) or the UV pin falls below its low
threshold (1.16V) the GATE voltage is immediately pulled low,
the PWRGD pin changes to its inactive state and the external
capacitor connected to the RAMP pin is discharged.
Calculations can be based on either the desired input voltage
operating limits or the input voltage shutdown limits. In the
following equations the shutdown limits are assumed.
The undervoltage and overvoltage shut down thresholds can be
programmed by means of the three resistor divider formed by
R1, R2 and R3. Since the input currents on the UV and OV pins
are negligible the resistor values may be calculated as follows:
UV
V
V
R
R
R
R
R
OV
V
V
R
R
R
R
OFF
UVL
EEUV off
OFF
OVH
EEOV off
=
=
=
+
+
+
=
=
=
+
+
1 16
2
3
1
2
3
1 26
3
1
2
3
.
.
(
)
(
)
Where |
V
EEUV(off)
| and |
V
EEOV(off)
| relative to V
EE
are Under & Over
Voltage Shut Down Threshold points.
If we select a divider current of 100A at a nominal operating
input voltage of 50 Volts then
R
R
R
1
2
3
50
100
500
+
+
=
=
V
A
k
From the second equation for an OV shut down threshold of 65V
the value of R3 may be calculated.
OV
R
R
OFF
=
=
=
=
1 26
65
3
500
3
1 26
500
65
9 69
.
k
.
k
.
k
The closest 1% value is 9.76k.
From the first equation for a UV shut down threshold of 35V the
value of R2 can be calculated.
UV
R
R
R
OFF
=
=
+
(
)
=
-
=
1 16
35
2
3
500
2
1 16
500
35
9 76
6 81
.
.
.
.
k
k
k
k
The closest 1% value is 6.81k.
Then
R
R
R
1
500
2
3
483
=
-
-
=
k
k
The closest 1% value is 487k.
6
HV301/HV311
From the calculated resistor values the OV and UV start up
threshold voltages can be calculated as follows:
UV
V
V
R
R
R
R
R
OV
V
V
R
R
R
R
ON
UVH
EEUV on
ON
OVL
EEOV on
=
=
=
+
+
+
=
=
=
+
+
1 26
2
3
1
2
3
1 16
3
1
2
3
.
.
(
)
(
)
Where |
V
EEUV(on)
| and |
V
EEOV(on)
|
are Under & Over Voltage Start
Up Threshold points relative to V
EE
.
Then
V
R
R
R
R
R
V
V
R
R
R
R
V
EEUV on
EEUV on
EEOV on
EEOV on
(
)
(
)
(
)
(
)
.
.
.
.
.
.
.
.
.
.
.
.
=
+
+
+
=
+
+
+
=
=
+
+
=
+
+
1 26
1
2
3
2
3
1 26
487
6 81
9 76
6 81
9 76
38 29
1 16
1
2
3
3
1 16
487
6 81
9 76
9 76
k
k
k
k
k
V
And
k
k
k
k
=
= 59 85
.
V
Therefore, the circuit will start when the input supply voltage is
in the range of 38.29V to 59.85V.
Design Information, cont'd.
Undervoltage/Overvoltage Operation
Programming Inrush and I
CB
(Circuit Breaker)
Method 1: Inrush independent of I
CB
Max Vt of a typical
power FET
GND
V
IN
Pass
Transistor
OFF
ON
UV
OFF
UV
ON
OV
OFF
OV
ON
V
SENSE
+ K
+
+
5k
2.5
A
7.5
A
10
A
10V
10n
0
A
0
A
RAMP
GATE
7.5
A
Vgs
Cgs
Cgd
C2
+
inrush
Rsense=12.5m
Cdb
(DRAIN)
Cload=100
F
Vin
dv
df
on Cramp constant
during limiting so no
current flowing into cap
gm(Vgs-Vt)
V
SENSE
VSENSE
5k
10V
10n=Cramp
RAMP
terminal
GATE
Termial
1 : 2
Isink
10
A
Internal Circuitry
mirror
C2
0.75nF
Rsense
Vsense
Cload
48V
10
A
1.
Choose circuit breaker trip point eg. 8A as follows
Rsense =
Choose inrush level, for example Inrush = 1A
3.
Calculate Isink
Inrush *Rsense
2.5 A
4.
Calculate C discharge limit
= 10 A -Isink = 7.5 A (typical) = iC
4a. Adjust for Auto - retry disable, if used
Vt
R
e.g.
4V
2.5M
= 1.6 A
e.g. iC = 10 A -Isink -1.6 A
2
2
max
disable
2
100
100
8
12 5
2
5
1
12 5
5
mV
I
mV
m
k
A
m
k
CB
=
=
=
=
=
.
.
.
In this example we assume Auto
In this example we assume Auto - retry is enabled so
ignore 1.6 A,
iC = 10 A -Isink = 7.5 A
5.
Note: i = C
iC = C
Inrush = C
Note V is fixed and V
is constant during limiting
across C
=
across C (as they share a
common node and their other terminals are fixed during inrush)
Inrush =
by conservation of charge on RAMP Node iC = 7.5 A
Inrush =
.
2
2
2
load
IN
RAMP
load
2
2
=
dv
dt
dv
dt
dv
dt
dv
dt
dv
dt
iC
C
Inrush
C
iC
C
C
A C
load
load
load
2
2
2
2
7 5
C
C
A C
Inrush
A
nF
A
load
2
7 5
7 5
100
1
=
C =
.
= 750pF = 0.75nF
Note that RAMP is protected by AC divider and Gate
is clamped internally.
2
.
7
HV301/HV311
The timing functions are defined by the following equations:
t
C
I
t
V
C
I
t
t
t
t
C
g
I
I
R
R
t
V
C
I
t
V
V
C
I
START
RAMP
RAMP
TH
GS th
RAMP
RAMP
POR
START
TH
RISE
RAMP
fs
RAMP
LIMIT
SENSE
FB
LIMIT
IN
LOAD
LIMIT
PWRGD
INT
GS
RAMP
RAMP
=
=
=
+
-
=
-
-
(
)
2 4
0 9
1 2
.
.
.
( )
(
)
LIMIT
Timing (Servo Mode)
Design Information, cont'd.
Programming Inrush and I
CB
, continued:
Method 2: Inrush = 1/2 I
CB
(Servo Mode)
i)
start with 2nF from gate to source
ii) increase to 10nF if needed
iii) add 1k series resistor from gate to capacitor if needed
Capacitor and/or
compensation resistor
will reduce peaking
GND
-48V
V
IN
I
IN
t
START
contact
bounce
I
LIM
PWRGD
V
UVL
t
RISE
t
PWRGD
V
GATE
Initialization
Limiting
Full On
V
GATE
V
OUT
t
LIM
t
TH
V
RAMP
V
RAMP
V
GATE
inactive
active
V
OUT
V
IN
V
GS(th)
V
GS(lim)
V
EE
t
POR
90%
1.
Choose I
=
100mV
R
e.g. 2A
R
= 50m
2.
Inrush =
50mv
R
, e.g.
50mV
50m
= 1A
3.
Add compensation components from gate to drain if
necessary to reduce peaking.
CB
SENSE
SENSE
SENSE
,
8
HV301/HV311
Start up Overload Protection
Start up must be achieved within a nominal 100ms as indicated
by the PWRGD pin transition to the active state or the circuit will
reset and an automatic restart will initiate. If there is an output
overload or short circuit during start up, the circuit will be in
current limit for the 100ms time limit (in servo mode). In feedback
capacitor mode the circuit breaker will shutdown the pass FET
before 100ms.
Circuit Breaker
The circuit breaker will trip in less than 5s when the voltage on
the SENSE pin reaches a nominal 100mV. A resistor in series
with the SENSE pin and a capacitor connected between the
SENSE and V
EE
pins may be added to delay the rate of voltage
rise on the SENSE pin, thus permitting a current overshoot and
delaying Circuit Breaker activation.
Automatic Restart
The automatic restart delay time is directly proportional to the
capacitance at the RAMP pin. Automatic restart sequence is
activated whenever the 100ms timeout is reached during start up
or the circuit breaker is tripped.
These equations assume that the load is purely capacitive and
the following definitions apply.
C
RAMP
is the external capacitor connected to the RAMP pin.
I
RAMP
is the output current from the RAMP pin, nominally
10A, when the voltage drop on R
SENSE
resistor is zero.
V
INT
is the internally regulated supply voltage and can range
from 8.5V to 12V.
V
GS(th)
is the gate threshold voltage of the external pass
transistor and may be obtained from its datasheet.
V
GS(limit)
is the external pass transistor gate-source voltage
required to obtain the limit current. It is dependent on the
pass transistor's characteristics and may be obtained from
the transfer characteristics on the transistor datasheet.
g
fs
is the transconductance of the external pass transistor
and may be obtained from its datasheet.
R
FB
is the internal feedback resistor and is nominally 5k.
I
LIMIT
is the load current when the voltage drop on the R
SENSE
resistor is 50mV.
These equations may be used to calculate the minimum value of
C
RAMP
for the most critical system performance characteristics.
For maximum contact bounce duration protection choose a
value for
t
POR
and use the following equation:
C
t
I
V
RAMP
POR
RAMP
GS th
=
+
2 4
.
( )
If control of PWRGD active delay is the critical system param-
eter, then choose a value for
t
PWRGD
and use the following
equation:
C
t
I
V
V
RAMP
PWRGD
RAMP
INT
GS
=
-
-
(
)
.
limit
1 2
Design Information, cont'd.
Auto-retry can be approximated as a
555-timer with 2.5A charge up and
charge down currents through 8V, to
a count of 256. Therefore,
T
=
2 8 256
2.5 A
C
AUTORETRY
ramp
Due to the 2.5A max charge current a resistor which draws
more than 2.5A below 8V will disable the autoretry. Try to
keep this resistor as big as possible, e.g. 2.5M, for most
MOSFETs with max V
t
of 4V this will vary the 10A Ramp
current source by only 4/2.5M=1.6A.
2.5
A
2.5
A
C
ramp
e.g.
2 8 256
2.5 A
Ion = 16.4s
9
HV301/HV311
Application Information
Supported External Pass Devices
The HV301 and HV311 are designed to support N-Channel
MOSFETs and IGBTs.
Selection of External Pass Devices
Since the current limit is likely to be set just slightly higher than
maximum continuous load current in a typical system, the
continuous current rating of the device will have to be at least
equal to the current limit value.
The
R
DS(ON)
of the device is likely to be selected based on
allowable voltage drop after the hot swap action has been
completed. Thus the continuous power dissipation rating of the
device can be determined from the following equation:
P
R
I
CONT
DS ON
LIMIT
=
(
)
2
The peak power rating may be calculated from the following
equation:
P
V
I
PEAK
IN
LIMIT
=
Given these values an external pass transistor may be selected
from the manufacturers data sheet.
Selection of Current Sense Resistor
The power rating of the sense resistor must be greater than
I
R
load
2
, where I
load
is the normal maximum operating load.
Kelvin Connection to Sense Resistor
Physical layout of the printed circuit board is critical for correct
current sensing. Ideally trace routing between the current sense
resistor and the V
EE
and SENSE pins should be direct and as
short as possible with zero current in the sense traces. The use
of Kelvin connection from SENSE pin and V
EE
pin to the respec-
tive ends of the current sense resistor is recommended.
Paralleling External Pass Transistors
Due to variations in threshold voltages and gain characteristics
between samples of transistors reliable 50% current sharing is
not achievable. Some measure of paralleling may be accom-
plished by adding resistors in series with the source of each
device; however, it will cause increased voltage drop and power
dissipation.
Paralleling of external Pass devices is not recommended!
If a sufficiently high current rated external pass transistor cannot
be found then increased current capability may be achieved by
connecting independent hotswap circuits in parallel, since they
act as current sources during the load capacitor charging time
when the circuits are in current limit. For this application the
HV301 with active high PWRGD is recommended where the
PWRGD pins of multiple hot swap circuits can be connected in
a wired OR configuration.
To Negative
Terminal of
Power Source
To Source
of MOSFET
To
V
EE
Pin
Sense Resistor
To
SENSE
Pin
10
HV301/HV311
Application Circuit 1
PWRGD Output
It is critical to have a detailed understanding of the ENABLE input
circuitry of the load (DC/DC PWM Converter) in order to make
the correct choice between the HV301 or HV311.
Many DC/DC PWM Converters reference their ENABLE inputs
to the negative input terminal. If the ENABLE input is active LOW
then the HV311 can be directly connected as shown below
(Application Circuit 1) since the open drain PWRGD output is
in a High-Z state until the external MOSFET is fully turned on and
the potential on the negative input of the converter is essentially
the same as the V
EE
pin of the HV311.
VDD
UV
OV
VEE
SENSE
GATE
RAMP
-48V
R4
12.5m
R1
487k
R2
6.81k
R3
9.76k
Q1
IRF530
Cload
+5V
HV311
8
3
2
COM
1
GND
C1
10nF
+
-
DC/DC
PWM
CONVERTER
PWRGD
ENABLE
5
7
4
6
Note: capacitor may be needed to slow PWRGD dv/dt if
oscillations are observed when V
IN
is close to OV.
11
HV301/HV311
Application Circuit 3
However, if the DC/DC PWM Converter with the ENABLE input
circuit configuration was active HIGH, then the apparent choice
of the HV301 would result in the creation of a current path
through the protective diode clamp of the ENABLE input and the
PWRGD output MOSFET of the HV301. For this situation the
HV311 should be used as shown below in Application Circuit 2.
In some applications the PWRGD signal is used to activate load
circuitry on the isolated output side of the DC/DC PWM Con-
verter. In this situation an optocoupler is needed to provide the
required isolation as shown below in Application Circuit 3.
Application Information, cont'd.
Application Circuit 2
VDD
UV
OV
VEE
SENSE
GATE
RAMP
-48V
Cload
+5V
HV311
8
3
2
5
7
4
COM
1
GND
+
-
DC/DC
PWM
CONVERTER
PWRGD
ENABLE
R4
12.5m
R1
487k
R2
6.81k
R3
9.76k
Q1
IRF530
C1
10nF
6
Note: capacitor may be needed to slow PWRGD dv/dt if
oscillations are observed when V
IN
is close to OV.
VDD
UV
OV
VEE
SENSE GATE
RAMP
-48V
Cload
+5V
HV311
8
3
2
COM
1
GND
Optocoupler
R4
12.5m
R1
487k
R2
6.81k
R3
9.76k
Q1
IRF530
C1
10nF
5
7
4
6
DC/DC
PWM
CONVERTER
PWRGD
ENABLE
Rload
Note: capacitor may be needed to slow PWRGD dv/dt if
oscillations are observed when V
IN
is close to OV.
12
HV301/HV311
When the details of the load ENABLE circuitry is not known,
using an optocoupler always provides a safe solution
(Application Circuit 4).
Application Information, cont'd.
Application Circuit 5
Filtering Voltage Spikes on Input Supply
In some systems over voltage spikes of very short duration may
exist. For these systems a small capacitor may be added from
the OV pin to the V
EE
pin to filter the voltage spikes (Application
Circuit 5).
Application Circuit 4
VDD
UV
OV
VEE
SENSE GATE
RAMP
-48V
Cload
+5V
HV311
8
3
2
COM
1
GND
Optocoupler
R4
60m
R1
487k
R2
6.81k
R3
9.76k
Q1
IRF530
C1
10nF
5
7
4
6
DC/DC
PWM
CONVERTER
PWRGD / PWRGD
ENABLE / ENABLE
Note: capacitor may be needed to slow PWRGD dv/dt if
oscillations are observed when V
IN
is close to OV.
VDD
UV
OV
VEE
SENSE GATE
RAMP
-48V
R4
12.5m
R1
487k
R2
6.81k
R3
9.76k
Q1
IRF530
Cload
+5V
HV301/
HV311
8
3
2
5
7
4
COM
1
GND
C1
10nF
C2
6
PWRGD / PWRGD
DC/DC
PWM
CONVERTER
ENABLE / ENABLE
Note: capacitor may be needed to slow PWRGD dv/dt if
oscillations are observed when V
IN
is close to OV.
13
HV301/HV311
Application Information, cont'd.
Application Circuit 7
Using Short Connector Pin
In some systems short connector pins are used to guarantee that
the power pins are fully mated before the hotswap control circuit
is enabled. For these systems the positive (V
DD
) end of the R1,
R2, and R3 resistor divider should be connected to the short pin
(Application Circuit 7).
Unfortunately this will also cause some delay in responding to
UV conditions. If this UV delay is not acceptable, then separate
resistor dividers can be provided for OV and UV with a capacitor
connected from OV pin to the V
EE
pin (Application Circuit 6).
Application Circuit 6
VDD
UV
OV
VEE
SENSE GATE
RAMP
-48V
R5
12.5m
R1
475k
R2
16.2k
R3
511k
Q1
IRF530
Cload
+5V
HV311
8
3
2
5
7
4
COM
1
GND
C1
10nF
C2
R4
10k
DC/DC
PWM
CONVERTER
PWRGD / PWRGD
ENABLE / ENABLE
6
Note: capacitor may be needed to slow PWRGD dv/dt if
oscillations are observed when V
IN
is close to OV.
VDD
UV
OV
VEE
SENSE GATE
RAMP
-48V
R4
12.5m
R1
487k
R2
6.81k
R3
9.76k
Q1
IRF530
Cload
+5V
HV301/
HV311
8
3
2
5
7
4
COM
1
GND
C1
10nF
Long
Pin
Short
Pin
Long
Pin
GND
6
DC/DC
PWM
CONVERTER
PWRGD / PWRGD
ENABLE / ENABLE
Note: capacitor may be needed to slow PWRGD dv/dt if
oscillations are observed when V
IN
is close to OV.
14
HV301/HV311
If separate resistor dividers are used for OV and UV, then only
the positive (V
DD
) end of the UV resistor divider should be
connected to the short pin (Application Circuit 8).
If a system requires the use of a short connector pin on the
negative supply lead to guarantee that the power pins are fully
Application Information, cont'd.
Application Circuit 9
Application Circuit 8
mated before the hotswap control circuit is enabled and a single
resistor divider string (R1, R2 and R3) is used, then a 6.2V to 10V
zener diode must be connected from the UV pin to the V
EE
pin,
as seen below in Application Circuit 9.
VDD
UV
OV
VEE SENSE GATE
RAMP
-48V
IRF530
R5
R1
475K
R2
16.2K
R3
511K
Q1
Cload
+5V
HV311
8
3
2
5
7
4
COM
1
GND
C1
10nF
12.5m
R4
10K
Long
Pin
Long
Pin
Short
Pin
GND
6
DC/DC
PWM
CONVERTER
PWRGD / PWRGD
ENABLE / ENABLE
Note: capacitor may be needed to slow PWRGD dv/dt if
oscillations are observed when V
IN
is close to OV.
VDD
UV
OV
VEE
SENSE GATE
RAMP
-48V
R4
12.5m
R1
487k
R2
6.81k
R3
9.76k
Q1
IRF530
Cload
+5V
HV311
8
3
2
5
7
6
4
COM
1
GND
C1
10nF
Long
Pin
Short
Pin
Long
Pin
-48V
6.2V
DC/DC
PWM
CONVERTER
PWRGD / PWRGD
ENABLE / ENABLE
Note: capacitor may be needed to slow PWRGD dv/dt if
oscillations are observed when V
IN
is close to OV.
15
HV301/HV311
Application Information, cont'd.
Application Circuit 11
Increasing Under Voltage Hysteresis
If the internally fixed under voltage hysteresis is insufficient for a
particular system application, then it may be increased by using
separate resistor dividers for OV and UV and providing a resistor
feedback path from the GATE pin to the UV pin (Application
Circuit 11).
If a system requires the use of a short connector pin on the
negative supply lead to guarantee that the power pins are fully
mated before the hotswap control circuit is enabled and uses
separate resistor dividers for UV and OV, then a 6.2V to 10V
zener diode must be connected from the OV pin to the V
EE
pin and
only the OV divider should be connected to the short pin
(Application Circuit 10).
Application Circuit 10
VDD
UV
OV
VEE
SENSE GATE
RAMP
-48V
R5
12.5m
R1
475k
R2
16.2k
R3
511k
Q1
IRF530
Cload
+5V
HV301/
HV311
8
3
2
5
7
4
COM
1
GND
C1
10nF
R4
10k
-48V
6.2V
Long
Pin
Short
Pin
Long
Pin
DC/DC
PWM
CONVERTER
PWRGD / PWRGD
ENABLE / ENABLE
6
Note: capacitor may be needed to slow PWRGD dv/dt if
oscillations are observed when V
IN
is close to OV.
VDD
UV
OV
VEE
SENSE GATE
RAMP
-48V
R5
12.5m
R1
475k
R2
16.2k
R3
511k
Q1
IRF530
Cload
+5V
HV301/
HV311
8
3
2
5
7
4
COM
1
GND
C1
10nF
R4
10k
R6
DC/DC
PWM
CONVERTER
PWRGD / PWRGD
ENABLE / ENABLE
6
Note: capacitor may be needed to slow PWRGD dv/dt if
oscillations are observed when V
IN
is close to OV.
16
HV301/HV311
Reverse Polarity Protection
The UV and OV pins are protected against reverse polarity input
supplies by internal clamping diodes and the fault currents are
sufficiently limited by the impedance of the external resistor
divider, however, a low current diode with a 100V breakdown
rating must be inserted in series with the V
DD
pin.
Application Information, cont'd.
This method (shown in Application Circuit 12) will protect the
hotswap control circuit however, due to the intrinsic diode in the
external MOSFET, the load will not be protected from reverse
polarity voltages.
Application Circuit 12
VDD
UV
OV
VEE
SENSE GATE
RAMP
-48V
R4
12.5m
R1
487k
R2
6.81k
R3
9.76k
Q1
IRF530
Cload
+5V
HV311
8
3
2
5
7
4
COM
1
GND
C1
10nF
D1
6
DC/DC
PWM
CONVERTER
PWRGD / PWRGD
ENABLE / ENABLE
Note: capacitor may be needed to slow PWRGD dv/dt if
oscillations are observed when V
IN
is close to OV.
17
HV301/HV311
Redundant Supplies
Many systems use redundant primary power supplies or battery
backup. When redundant AC powered sources are used they are
generally diode OR'ed to the load on the hot terminal.
For these systems, the use of independent hotswap controllers
is recommended with the diode OR'ing provided after the hotswap
Application Information, cont'd.
controllers. The HV311 is ideally suited for such applications
since two or more active low PWRGD signals can be connected
to a single active low ENABLE pin, thus enabling the load as long
as at least one primary power source is available. By adding low
current 100V diodes in series with the V
DD
pins, full reverse
polarity protection on either power source is also provided
(Application Circuit 13).
Application Circuit 13
VDD
UV
OV
VEE
SENSE GATE
RAMP
-48V
Cload
+5V
8
3
2
COM
1
GND
VDD
UV
OV
VEE
SENSE GATE
RAMP
-48V
R4
60m
R1
487k
R2
6.81k
R3
9.76k
Q1
IRF530
8
3
2
5
7
4
1
GND
C1
10nF
D1
D1
D2
D2
PS1
PS2
HV301/
HV311
HV301/
HV311
PWRGD
6
PWRGD
R1
487k
R2
6.81k
R3
9.76k
5
7
4
6
R4
60m
Q1
IRF530
C1
10nF
DC/DC
PWM
CONVERTER
ENABLE / ENABLE
Note: capacitor may be needed to slow PWRGD dv/dt if
oscillations are observed when V
IN
is close to OV.
18
HV301/HV311
Application Information, cont'd.
Use with Negative Ground
Either the HV301 or HV311 may be used with any negative
ground systems where DC/DC PWM Converters have isolated
outputs and their inputs need not be ground referenced
(Application Circuit 14).
Application Circuit 14
Current Limit Stability (Method 2 (Servo) Only)
The closed loop current mode control system used in the HV301/
HV311 is very stable, especially when driving MOSFETs with
high gate capacitances (C
ISS
). However, a peaking in I
LIMIT
near
the end of the current limit may be noted with some MOSFETs.
The current control loop can be frequency compensated to
eliminate this peaking by adding a series connected capacitor
and resistor between the gate and source of the external MOSFET.
The recommended starting values for C and R are 10nF and 1K.
These compensation values should be verified by board level
testing, which may yield satisfactory results with reduced com-
ponent values.
VDD
UV
OV
VEE
SENSE GATE
RAMP
+48V
Cload
+5V
HV301/
HV311
8
3
2
COM
1
GND
R4
12.5m
R1
487k
R2
6.81k
R3
9.76k
Q1
IRF530
C1
10nF
DC/DC PWM CONVERTER
PWRGD / PWRGD
ENABLE/ ENABLE
5
7
4
6
Note: capacitor may be needed to slow PWRGD dv/dt if
oscillations are observed when V
IN
is close to OV.
19
HV301/HV311
Application Information cont'd.
Extending Circuit Breaker Delay
Connecting a resistor in series with the SENSE pin and a
capacitor between the SENSE and V
EE
pins as shown in the
following diagram may be used to extend the Circuit Breaker
delay time beyond the 5s internally set delay time (Application
Circuit 15).
The time delay achievable by this method is limited since this
Application Circuit 15
delay circuit will also effect the current control feedback loop and
will result in a current overshoot during the external pass device
turn on transition to current limit. If the time delay required for the
Circuit Breaker causes excessive current overshoot during the
turn on transition then the following circuit may be used, where
the RC filter is switched on after the completion of the current
limit control function of the hotswap controller.
VDD
UV
OV
VEE
SENSE GATE
RAMP
-48V
Cload
+5V
HV301/
HV311
8
3
2
COM
1
GND
C2
R5
DC/DC
PWM
CONVERTER
PWRGD / PWRGD
ENABLE/ ENABLE
R4
12.5m
R1
487k
R2
6.81k
R3
9.76k
Q1
IRF530
5
7
4
6
Note: capacitor may be needed to slow PWRGD dv/dt if
oscillations are observed when V
IN
is close to OV.
20
HV301/HV311
Application Information cont'd.
Latched Operation
For those applications that need to disable the automatic retry
capability, the following circuit disables the auto retry feature.
Application Circuit 17
VDD
UV
OV
VEE
SENSE GATE
RAMP
-48V
Cload
+5V
HV301 / HV311
8
3
2
COM
1
GND
PWRGD / PWRGD
ENABLE / ENABLE
DC/DC
PWM
CONVERTER
6
4
5
7
R1
487k
R2
6.81k
R3
9.76k
R4
12.5m
Q1
IRF530
2.5M
Note: capacitor may be needed to slow PWRGD dv/dt if
oscillations are observed when V
IN
is close to OV.
21
HV301/HV311
1235 Bordeaux Drive, Sunnyvale, CA 94089
TEL: (408) 744-0100 FAX: (408) 222-4895
www.supertex.com
08/26/02 rev.11b
2002 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
Package Dimensions
0
8
45
7
(4 PLCS)
0.193
0.012
(4.90
0.30)
D
0.192
0.005
(4.89
0.11)
H
1
0.154
0.004
(3.91
0.10)
E
0.236
0.008
(5.99
0.20)
H
0.061
0.008
(1.55
0.20)
A
0.007
0.003
(0.178
0.076)
A
1
TYP.
0.050
(1.20)
e
0.016
0.002
(0.406
0.05)
B
C
0.010
0.002
(0.254
0.051)
0.035
0.015
(0.889
0.381)
L
h
0.020
0.009
(0.508
0.229)
L
1
0.0275
0.0025
(0.698
0.064)
Circled letters (e.g. denote JEDEC reference dimensons.
B
Inches
(Millimeters)
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