1
12/13/01
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
Package Options
Recommended
80-Lead
80-Lead
Device
Operating
Quad Cerpak
Quad Plastic
Die
V
PP
Max
Gullwing
Gullwing
HV3418
180V
HV3418DG
HV3418PG
HV3418X
HV3418
64-Channel Serial To Parallel Converter
With High Voltage Push-Pull Outputs
Ordering Information
General Description
The HV34 is a low voltage serial to high voltage parallel converter
with push-pull outputs. This device has been designed for use as
a printer driver for inkjet applications. It can also be used in any
application requiring multiple output high voltage, low current
sourcing and sinking capabilities.
The device consists of a 64-bit shift register, 64 latches, and
control logic to perform the polarity select and blanking of the
outputs. A DIR pin controls the direction of data shift through the
device. With DIR grounded, D
IOA
is Data-In and D
IOB
is Data-Out;
data is shifted from HV
OUT
64 to HV
OUT
1. When DIR is at logic high,
D
IOB
is Data-In and D
IOA
is Data-Out: data is then shifted from
HV
OUT
1 to HV
OUT
64. Data is shifted through the shift register on
the low to high transition of the clock. Data output buffers are
provided for cascading devices. Operation of the shift register is
not affected by the LE (latch enable), BL (blanking), or the POL
(polarity) inputs. Transfer of data from the shift register to the latch
occurs when the LE (latch enable) is high. The data in the latch is
stored during LE transition from high to low.
Features
HVCMOS
technology
Output voltages up to 180V
Low power level shifting
Shift register speed: 6MHz @ V
DD
= 5V
12MHz @ V
DD
= 12V
Latched data outputs
Output polarity and blanking
CMOS compatible inputs
Forward and reverse shifting options
Absolute Maximum Ratings
1
Supply voltage, V
DD
-0.5V to +15V
Supply voltage, V
PP
V
DD
to +200V
Logic input levels
-0.5V to V
DD
+0.5V
Ground current
2
1.5A
High voltage supply current
2
1.3A
Continuous total power dissipation
3
Ceramic
1900mW
Plastic
1200mW
Operating temperature range
Ceramic -55C to +125C
Plastic
-40C to +85C
Storage temperature range
-65C to +150C
Notes:
1. All voltages are referenced to GND.
2. Connection to all power and ground pads is required. Duty cycle is limited by
the total power dissipated in the package.
3. For operation above 25C ambient derate linearly to maximum operating
temperature at 20mW/C for plastic and at 31.7mW/C for ceramic.
2
Symbol
Parameter
Min
Typ
Max
Units
V
DD
Logic supply voltage
V
DD
= 5V
4.5
5.0
5.5
V
V
DD
=12V
10.8
12.0
13.2
V
V
PP
High voltage supply
60
180
V
V
IH
High-level input voltage
V
DD
-0.9
V
DD
V
V
IL
Low-level input voltage
0
0.9
V
T
A
Operating free-air temperature
Plastic
-40
+85
C
Ceramic
-55
+125
Notes:
Power-up sequence should be the following:
1. Connect ground.
4. Apply V
PP
.
2. Apply V
DD
.
5. The V
PP
should not drop below V
DD
or float during operation.
3. Set all inputs (Data, CLK, Enable, etc.) to a known state.
Power-down sequence should be the reverse of the above.
Symbol
Parameter
Min
Typ
Max
Units
Conditions
f
CLK
Clock Frequency
12(6)
MHz
t
W
Clock Width High and Low
High
40(83)
ns
t
SU
Data Setup Time Before Clock Rises
25(35)
ns
t
H
Data Hold Time After Clock Rises
10(30)
ns
t
WLE
Width of Latch Enable Pulse
62(80)
ns
t
DLE
LE Delay Time Rising Edge of Clock
25(35)
ns
t
SLE
LE Setup Time Before Rising Edge of Clock
30(40)
ns
t
ON
, t
OFF
Time from Latch Enable to HV
OUT
1(1.5)
s
C
L
= 20pF
t
DHL
Delay Time Clock to Data High to Low
50(110)
ns
C
L
= 20pF
t
DLH
Delay Time Clock to Data Low to High
75(160)
ns
C
L
= 20pF
t
r
, t
f
All Logic Inputs
5
ns
Notes:
1. Shift register speed can be as low as DC as long as Data Set-up and Hold Time meet the spec.
2. AC Characteristics are guaranteed only under V
DD
= 12V and V
DD
= 5V.
Electrical Characteristics
(over recommended operating conditions unless noted)
Symbol
Parameter
Min
Typ
Max
Units
Conditions
I
DD
V
DD
Supply Current
25
mA
f
CLK
= 12MHz, f
DATA
= 12MHz
LE = LOW
I
DDQ
Quiescent V
DD
Supply Current
200
A
All V
IN
= 0V or V
DD
I
PP
High Voltage Supply Current
0.50
mA
V
PP
= 180V All outputs high
0.50
mA
V
PP
= 180V All outputs low
I
IH
High-Level Logic Input Current
10
A
V
IH
= V
DD
I
IL
Low-Level Logic Input Current
-10
A
V
IL
= 0V
V
OH
High-Level Output
HV
OUT
155
V
V
PP
= 180V, IHV
OUT
= -5mA
Data Out
V
DD
-1V
V
ID
OUT
= -100A
V
OL
Low-Level Output
HV
OUT
25
V
V
PP
= 180V, IHV
OUT
= +5mA
Data Out
1.0
V
ID
OUT
= +100A
V
OC
HV
OUT
Clamp Voltage
V
PP
+1.5
V
I
OL
= +5mA
-1.5
V
I
OL
= -5mA
DC Characteristics
Recommended Operating Conditions
AC Characteristics
1,2
(For V
DD
= 12V: values in parentheses are for V
DD
= 5V; V
PP
= 180V, T
A
= 25C)
HV3418
3
HV3418
Latch Enable
HV
OUT
w/ S/R LOW
Data Valid
50%
50%
Data Input
Clock
D
IO
/D
OI
50%
50%
50%
t
SU
t
H
t
WL
t
WH
50%
50%
t
DLH
t
DHL
50%
t
WLE
t
DLE
t
SLE
50%
50%
t
ON
10%
HV
OUT
w/ S/R HIGH
90%
90%
10%
t
OFF
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
OH
V
OL
V
IH
V
OL
V
OH
V
OL
V
OH
V
OL
V
DD
Input
GND
V
PP
GND
HV
OUT
Logic Inputs
GND
Data Out
Logic Data Output
High Voltage Outputs
V
DD
Input and Output Equivalent Circuits
Switching Waveforms
4
HV3418
HV
OUT
2
60 Additional
Outputs
POL
BL
Latch Enable
Clock
64 bit
Static Shift
Register
64 Latches
HV
OUT
63
V
PP
HV
OUT
1
DIR
HV
OUT
64
D
IOB
D
IOA
Inputs
Outputs
Function
Shift Reg
HV Outputs
Data Out
1
2...64
1
2...64
*
All on
X
X
X
L
L
X
*
*...*
H
H...H
*
All off
X
X
X
L
H
X
*
*...*
L
L...L
*
Invert mode
X
X
L
H
L
X
*
*...*
*
*...*
*
Load S/R
H or L
L
H
H
X
H or L *...*
*
*...*
*
X
X
H
H
X
*
*...*
*
*...*
*
X
X
H
L
X
*
*...*
*
*...*
*
L
H
H
H
X
L
*...*
L
*...*
*
H
H
H
H
X
H
*...*
H
*...*
*
D
IOA
X
X
X
L
Q
n
Q
n-1
--
D
IOB
D
IOB
X
X
X
H
Q
n
Q
n+1
--
D
IOA
Notes:
H = high level, L = low level, X = irrelevant, = low-to-high transition, = high-to-low transition.
* = dependent on previous stage's state before the last CLK or last LE high.
Data
CLK
LE
BL
POL
DIR
Load/Store Data
in Latches
Transparent
Latch mode
Function Table
I/O Relation
Functional Block Diagram
5
65
80
1
24
25
40
41
64
Index
top view
80-pin Gullwing Package
Pin Configurations
Package Outline
HV34
Pin
Function
Pin
Function
1
HV
OUT
41/24
41
HV
OUT
1/64
2
HV
OUT
42/23
42
HV
OUT
2/63
3
HV
OUT
43/22
43
HV
OUT
3/62
4
HV
OUT
44/21
44
HV
OUT
4/61
5
HV
OUT
45/20
45
HV
OUT
5/60
6
HV
OUT
46/19
46
HV
OUT
6/59
7
HV
OUT
47/18
47
HV
OUT
7/58
8
HV
OUT
48/17
48
HV
OUT
8/57
9
HV
OUT
49/16
49
HV
OUT
9/56
10
HV
OUT
50/15
50
HV
OUT
10/55
11
HV
OUT
51/14
51
HV
OUT
11/54
12
HV
OUT
52/13
52
HV
OUT
12/53
13
HV
OUT
53/12
53
HV
OUT
13/52
14
HV
OUT
54/11
54
HV
OUT
14/51
15
HV
OUT
55/10
55
HV
OUT
15/50
16
HV
OUT
56/9
56
HV
OUT
16/49
17
HV
OUT
57/8
57
HV
OUT
17/48
18
HV
OUT
58/7
58
HV
OUT
18/47
19
HV
OUT
59/6
59
HV
OUT
19/46
20
HV
OUT
60/5
60
HV
OUT
20/45
21
HV
OUT
61/4
61
HV
OUT
21/44
22
HV
OUT
62/3
62
HV
OUT
22/43
23
HV
OUT
63/2
63
HV
OUT
23/42
24
HV
OUT
64/1
64
HV
OUT
24/41
25
V
PP
65
HV
OUT
25/40
26
D
IOA
66
HV
OUT
26/39
27
N/C
67
HV
OUT
27/38
28
N/C
68
HV
OUT
28/37
29
BL
69
HV
OUT
29/36
30
POL
70
HV
OUT
30/35
31
V
DD
71
HV
OUT
31/34
32
DIR
72
HV
OUT
32/33
33
LGND
73
HV
OUT
33/32
34
OGND
74
HV
OUT
34/31
35
N/C
75
HV
OUT
35/30
36
N/C
76
HV
OUT
36/29
37
CLK
77
HV
OUT
37/28
38
LE
78
HV
OUT
38/27
39
D
IOB
79
HV
OUT
39/26
40
V
PP
80
HV
OUT
40/25
Note:
Pin designation for DIR = H/L
Example: for DIR = H, Pin 1 is HV
OUT
41
for DIR = L, Pin 1 is HV
OUT
24
HV3418
1235 Bordeaux Drive, Sunnyvale, CA 94089
TEL: (408) 744-0100 FAX: (408) 222-4895
www.supertex.com
12/13/010
2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
PDF 
ZIP