1
HV514
08/08/03
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
HV514
8-Channel Serial to Parallel Converter
with High Voltage Push-Pull Outputs
Features
HVCMOS, technology
Operating output voltage of 250V
Low power level shifting from 5V to 250V
Shift clock speed 8MHz @ V
DD
=5V
8 latch data outputs
Output blanking
CMOS compatible inputs
Programmable POL latch
Applications
Piezoelectric transducer driver
Weaving applications
Braille
Printers
MEMs
Displays
General Description
The HV514 is a low voltage serial to high voltage parallel
converter with 8 high voltage push-pull outputs. This device has
been designed to drive small capacitve loads such as piezoelec-
tric transducers. It can also be used in any application requiring
multiple high voltage outputs, medium current sourcing and
sinking capabilities.
The device consists of an 8-bit shift register, dual 8-bit latches,
and control logic to latch data, and control blanking of the
outputs. Data is shifted through the shift register on the rising
transition of the clock. A data output buffer is provided for
cascading devices. Operation of the shift register is not affected
by the /LE, SEL, or the /BL inputs. Transfer of data from the shift
register to the latch occurs when the /LE is high. Shift register
data is shifted to the 8-bit Data Latch when SEL is high; and shift
register data is shifted to the 8-bit Polarity Latch when SEL is low.
The data is held in the output latches whenever /LE is low.
The high voltage output state is primarily dependent on the value
in the polarity latch. If the blank, /BL, is low, the output condition
is the result of a 1 being exclusively-NOR'ed with the polarity
latch value. If /BL is high, the output condition is the result of the
data latch being exclusively-NOR'ed with the polarity latch.
All outputs with have a break-before-make circuitry to reduce
cross-over current during output state changes.
Note: /LE, SEL, and /BL have internal 20k-ohm pull-up resistors.
8-bit shift register
2 x 8-bit latc
h
Output contr
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Le
vel translator
8
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DD
V
PP
D
IN
CLK
D
OUT
GND
LE*
BL*
SEL
HV
OUT
1
HV
OUT
8
Top Block Diagram
2
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Absolute Maximum Ratings*
Supply Voltage, V
DD
-0.5V to 6V
Supply Voltage, V
PP
275V
Logic input levels
-0.5V to V
DD
+0.5V
Ground current
0.3A
High voltage supply current
0.25A
Continuous total power dissipation
750mW
Operating temperature range
-40C to +85C
Storage temperature range
-65C +150C
* All voltages are referenced to device ground.
Device
Part Number
Package
Die
HV514
HV514WG
24 Lead SOW
HV514X
Ordering Information
3
HV514
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C
Notes:
1. Below minimum V
PP
the output may not switch.
2. Power-up sequence should be the following:
1. Connect ground.
2. Apply V
DD
.
3. Set all inputs (Data, CLK, Enable, etc.) to a known state.
4. Apply V
PP
.
Power-down sequence should be the reverse of the above.
Input and Output Equivalent Circuits
V
DD
Input
GND
V
PP
HV
GND
HV
OUT
Logic Inputs
GND
Data Out
Logic Data Output
High Voltage Outputs
V
DD
*
20k
*
BL, SEL, LE
Note: There is an internal output resistor for the high voltage output pin for SOA protection
4
HV514
Switching Waveforms
LE
HV
OUT
w/ S/R LOW
Data Valid
50%
50%
Data Input
CLK
Data Out
50%
50%
50%
t
SU
t
H
t
WL
t
WH
50%
t
DLH
t
DHL
50%
t
WLE
t
DLE
t
SLE
50%
50%
t
d
ON
10%
HV
OUT
w/ S/R HIGH
90%
90%
10%
t
d
OFF
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
OH
V
OL
V
IH
V
OL
V
OH
V
OL
V
OH
V
OL
50%
t
R
t
F
/BL, /LE, and SEL hav internal 20k pull-up resistors.
Functional Block Diagram
8-bit
SHIFT
REGISTER
SR1
SR8
DIN
CLK
D
OUT
D1
D8
LE
LE
P1
P8
8-bit
DATA
LATCH
8-bit
POLARITY
LATCH
SEL
LE
BL
HV
OUT1
HV
OUT8
Note: BL, SEL, and LE have internal 20k
pull-up resistors.
L/T
L/T
6
HV514
1235 Bordeaux Drive, Sunnyvale, CA 94089
TEL: (408) 222-8888 FAX: (408) 222-4895
www.supertex.com
08/08/03
2003 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
Package Outline
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
20-Lead SOW Package (WG)
WIde Body
Pin Configuration
Pin
Function
1
CLK
2
LE
3
D
IN
4
LGND
5
HVGND
6
HVGND
7
HV
out
1
8
HV
out
2
9
HV
out
3
10
HV
out
4
11
HV
out
5
12
HV
out
6
13
HV
out
7
14
HV
out
8
15
V
PP
16
V
PP
17
V
DD
18
D
OUT
19
BL
20
SEL
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