1
02/96/022
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
HV57708
Device
80 Lead Quad
80 Lead Quad
80 Lead Quad
Ceramic Gullwing
Plastic Gullwing
Ceramic Gullwing
Die
(MIL-STD-883 Processed*)
(MIL-STD-883 Processed*)
HV57708
HV57708DG
HV57708PG
RBHV57708DG
HV57708X
* For Hi-Rel process flows, refer to page 5-3 of the Databook.
32 MHz, 64-Channel Serial To Parallel Converter
With Push-Pull Outputs
Ordering Information
Package Options
General Description
The HV577 is a low-voltage serial to high-voltage parallel con-
verter with push-pull outputs. This device has been designed for
use as a driver for electroluminescent displays. It can also be used
in any application requiring multiple output high-voltage current
sourcing and sinking capability such as driving plasma panels,
vacuum fluorescent displays, or large matrix LCD displays.
The device has 4 parallel 16-bit shift registers, permitting data
rates 4X the speed of one ( they are clocked together). There are
also 64 latches and control logic to perform the polarity select and
blanking of the outputs. HVout1 is connected to the first stage of
the first shift register through the polarity and blanking logic. Data
is shifted through the shift registers on the logic low to high
transition of the clock. The DIR pin causes CCW shifting when
connected to GND, and CW shifting when connected to V
DD
. A
data output buffer is provided for cascading devices. This output
reflects the current status of the last bit of the shift register
(HV
OUT
64). Operation of the shift register is not affected by the LE
(latch enable), BL (blanking), or the POL (polarity) inputs. Trans-
fer of data from the shift registers to the latches occurs when the
LE (latch enable) input is high. The data in the latches is stored
when LE is low.
Features
Processed with HVCMOS
technology
5V CMOS logic
Output voltages up to 80V
Low power level shifting
32MHz equivalent data rate
Latched data outputs
Forward and reverse shifting options (DIR pin)
Diode to V
PP
allows efficient power recovery
Outputs may be hot switched
Hi-Rel processing available
Absolute Maximum Ratings
Supply voltage, V
DD
1
-0.5V to +7.5V
Output voltage, V
PP
1
-0.5V to +90V
Logic input levels
1
-0.3V to V
DD
+0.3V
Ground current
2
1.5A
Continuous total power dissipation
3
Plastic
1200mW
Ceramic
1900mW
Operating temperature range
Plastic
-40 to 85
C
Ceramic
-55
C to 125
C
Storage temperature range
-65
C to +150
C
Lead temperature 1.6mm (1/16 inch)
260
C
from case for 10 seconds
Notes:
1. All voltages are referenced to GND.
2. Limited by the total power dissipated in the package.
3. For operation above 25
C ambient derate linearly to maximum operating
temperature at 20mW/
C for plastic and at 19mW/
C for ceramic.
For detailed circuit and application information, please refer
to application note AN-H3.
2
Symbol
Parameter
Min
Max
Units
V
DD
Logic supply voltage
4.5
5.5
V
V
PP
Output voltage
8
80
V
V
IH
High-level input voltage
V
DD
-0.5V
V
V
IL
Low-level input voltage
0
0.5
V
f
CLK
Clock frequency per register
8
MHz
T
A
Operating free-air temperature
Plastic
-40
+85
C
Ceramic
-55
+125
Note: Power-up sequence should be the following:
1. Connect ground.
2. Apply V
DD
.
3. Set all inputs (Data, CLK, Enable, etc.) to a known state.
4. Apply V
PP
.
5. The V
PP
should not drop below V
DD
or float during operation.
Power-down sequence should be the reverse of the above.
Electrical Characteristics
(over recommended operating conditions unless noted, T
A
=-40
C to +85
C)
DC Characteristics
Symbol
Parameter
Min
Max
Units
Conditions
I
DD
V
DD
supply current
15
mA
V
DD
= V
DD
max
f
CLK
= 8MHz
I
PP
High voltage supply current
100
A
Outputs high
100
A
Outputs low
I
DDQ
Quiescent V
DD
supply current
100
A
All V
IN
= V
DD
V
OH
High-level output
HV
OUT
65
V
I
O
= -15mA, V
PP
= 80V
Data out
V
DD
- 0.5
V
I
O
= -100
A
V
OL
Low-level output
HV
OUT
7
V
I
O
= 12mA, V
PP
= 80V
Data out
0.5
V
I
O
= 100
A
I
IH
High-level logic input current
1
A
V
IH
= V
DD
I
IL
Low-level logic input current
-1
A
V
IL
= 0V
V
OC
High voltage clamp diode
1
V
I
OC
= 1mA
Recommended Operating Conditions
AC Characteristics
(T
A
= 85
C max. Logic signal inputs and Data inputs have t
r
, t
f
5ns [10% and 90% points])
Symbol
Parameter
Min
Max
Units
Conditions
f
CLK
Clock frequency
8
MHz
Per Register
t
WL
,t
WH
Clock width high or low
62
ns
t
SU
Data set-up time before clock rises
10
ns
t
H
Data hold time after clock rises
15
ns
t
ON
, t
OFF
Time from latch enable to HV
OUT
500
ns
C
L
= 15pF
t
DHL
Delay time clock to data high to low
70
ns
C
L
= 15pF
t
DLH
Delay time clock to data low to high
70
ns
C
L
= 15pF
t
DLE
*
Delay time clock to LE low to high
25
ns
t
WLE
Width of LE pulse
25
ns
t
SLE
LE set-up time before clock rises
0
ns
*
t
DLE
is not required but is recommended to produce stable HV outputs and thus minimize power dissipation and current spikes (allows internal SR output to stabilize).
HV57708
3
HV57708
Latch Enable
HV
OUT
w/ S/R LOW
Data Valid
50%
50%
Data Input
Clock
Data Out
50%
50%
50%
t
SU
t
H
t
WL
t
WH
50%
t
DLH
t
DHL
50%
t
WLE
t
DLE
t
SLE
50%
50%
t
ON
10%
HV
OUT
w/ S/R HIGH
90%
90%
10%
t
OFF
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
OH
V
OL
V
IH
V
OL
V
OH
V
OL
V
OH
V
OL
10%
90%
90%
10%
50%
t
f
t
r
V
DD
Input
GND
V
PP
GND
HV
OUT
Logic Inputs
GND
Data Out
Logic Data Output
High Voltage Outputs
V
DD
Input and Output Equivalent Circuits
Switching Waveforms
4
HV57708
HV 3
7
11
HV 63
HV 4
8
12
HV 64
HV 2
6
10
HV 62
HV 1
5
9
HV 61
POL
PP
V
OUT
BL
D 4
OUT
OUT
OUT
OUT
OUT
OUT
OUT
LE
I
D 4
O
SR4
SR3
SR2
SR1
CLK
DIR
GND
DD
V
D 3
O
D 2
O
D 1
O
D 3
I
D 2
I
D 1
I
D 1
O
D 2
O
D 3
O
D 4
O
D 1
I
D 2
I
D 3
I
D 4
I
Functional Block Diagram
Inputs
Outputs
Function
Shift Reg
HV Outputs
Data Out
All O/P High
X
X
X
L
L
X
H
All O/P Low
X
X
X
L
H
X
L
O/P Normal
X
X
X
H
H
X
No inversion
O/P Inverted
X
X
X
H
L
X
Inversion
L
H
H
H
X
L
L
H
H
H
H
X
H
H
L
H
H
L
X
L
H
H
H
H
L
X
H
L
Data Stored/
X
X
L
H
H
X
*
Stored Data
Latches Loaded
X
X
L
H
L
X
*
Inversion of
Stored Data
D
I/O
1-4A
H
H
H
H
Q
n
Q
n +1
New H or L
D
I/O
1 4B
D
I/O
1-4A
L
H
H
H
Q
n
Q
n +1
Previous
D
I/O
1 4B
H or L
D
I/O
1-4B
L
H
H
L
Q
n
Q
n -1
Previous
D
I/O
1 4A
H or L
D
I/O
1-4B
H
H
H
L
Q
n
Q
n -1
New H or L
D
I/O
1 4A
Data
CLK
LE
BL
POL
DIR
Note:
*
= dependent on previous stage's state. See Pin configuration for D
IN
and D
OUT
pin designation for CW and CCW shift.
Function Table
I/O Relation
Note: Each SR (shift register) provides 16 outputs. SR1 supplies every fourth output starting with 1; SR2 supplies every fourth output with 2, etc.
Data Falls
Through
(Latches
Transparent)
5
1235 Bordeaux Drive, Sunnyvale, CA 94089
TEL: (408) 744-0100 FAX: (408) 222-4895
www.supertex.com
02/06//02
2002 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
HV57708
65
80
1
24
25
40
41
64
Index
top view
80-pin Gullwing Package
4
2
3
3
2
25 26 27 28
36 37 38 39
4
DIR = H
DIR = L
DIR = H; CW (HV
OUT
1
HV
OUT
64)
DIR = L; CCW (HV
OUT
64
HV
OUT
1)
HV
OUT
32
HV
OUT
2
HV
OUT
1
H
OUT
33
H
OUT
63
H
OUT
64
Pin
1
1
SR1
SR2
SR3
SR4
Pin Configurations
HV577
80-pin Gullwing
Pin
Function
1
HV
OUT
24/41
2
HV
OUT
23/42
3
HV
OUT
22/43
4
HV
OUT
21/44
5
HV
OUT
20/45
6
HV
OUT
19/46
7
HV
OUT
18/47
8
HV
OUT
17/48
9
HV
OUT
16/49
10
HV
OUT
15/50
11
HV
OUT
14/51
12
HV
OUT
13/52
13
HV
OUT
12/53
14
HV
OUT
11/54
15
HV
OUT
10/55
16
HV
OUT
9/56
17
HV
OUT
8/57
18
HV
OUT
7/58
19
HV
OUT
6/59
20
HV
OUT
5/60
21
HV
OUT
4/61
22
HV
OUT
3/62
23
HV
OUT
2/63
24
HV
OUT
1/64
25
D
IN
1/D
OUT
4(A)
26
D
IN
2/D
OUT
3(A)
27
D
IN
3/D
OUT
2(A)
28
D
IN
4/D
OUT
1(A)
29
LE
30
CLK
31
BL
32
V
DD
33
DIR
34
GND
35
POL
36
D
OUT
4/D
IN
1(B)
37
D
OUT
3/D
IN
2(B)
38
D
OUT
2/D
IN
3(B)
39
D
OUT
1/D
IN
4(B)
40
V
PP
Package Outline
Note: Pin designation for DIR = H/L.
Example: For DIR = H, pin 41 is HV
OUT
64.
For DIR = L, pin 41 is HV
OUT
1.
For CW/CCW Shift see function table Q
N
Q
N
+1.
41
HV
OUT
64/1
42
HV
OUT
63/2
43
HV
OUT
62/3
44
HV
OUT
61/4
45
HV
OUT
60/5
46
HV
OUT
59/6
47
HV
OUT
58/7
48
HV
OUT
57/8
49
HV
OUT
56/9
50
HV
OUT
55/10
51
HV
OUT
54/11
52
HV
OUT
53/12
53
HV
OUT
52/13
54
HV
OUT
51/14
55
HV
OUT
50/15
56
HV
OUT
49/16
57
HV
OUT
48/17
58
HV
OUT
47/18
59
HV
OUT
46/19
60
HV
OUT
45/20
61
HV
OUT
44/21
62
HV
OUT
43/22
63
HV
OUT
42/23
64
HV
OUT
41/24
65
HV
OUT
40/25
66
HV
OUT
39/26
67
HV
OUT
38/27
68
HV
OUT
37/28
69
HV
OUT
36/29
70
HV
OUT
35/30
71
HV
OUT
34/31
72
HV
OUT
33/32
73
HV
OUT
32/33
74
HV
OUT
31/34
75
HV
OUT
30/35
76
HV
OUT
29/36
77
HV
OUT
28/37
78
HV
OUT
27/38
79
HV
OUT
26/39
80
HV
OUT
25/40
Pin
Function
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