12-122

HV623

32-Channel 128-Level Amplitude Gray-Shade

Display Column Driver

Absolute Maximum Ratings

Supply voltage, V

-0.5V to +7.5V

Supply voltage, V

-0.5V to +90V

Logic input levels

-0.5 to V

+ 0.5V

Ground current

1.5A

Continuous total power dissipation

Operating temperature range

-40

C to +70

Storage temperature range

-65

C to +150

Lead temperature 1.6mm (1/16 inch)

260

from case for 10 seconds

Notes:
1. All voltages are referenced to GND.
2. Duty cycle is limited by the total power dissipated in the package.
3. For operation above 25

C ambient derate linearly to 70

C at 22.2mW/

Features

5V CMOS inputs

Up to 80V modulation voltage

Capable of 128 levels of gray shading

20MHz data throughput rate

32 outputs per device (can be cascaded)

Pin-programmable shift direction (DIR)

D/A conversion cycle time is 32

Diodes in output structure allow usage
in energy recovery systems

Integrated HVCMOS

technology

Available in 3-sided 64-lead gullwing package

General Description

The HV623 is a 32-channel driver IC for gray shade display use.
It is designed to produce varying output voltages between 3 and
80 volts. This amplitude modulation at the output is facilitated by
an external ramp voltage V

. See Theory of Operation for detailed

explanation.

This device consists of a dual 16-bit shift registers, 32 data latches
and comparators, and control logic to preform 128 levels of gray
shading. There are 7 bits of data inputs. Data is shifted through the
shift registers at both edges of the clock, resulting a data transfer
rate of twice of the shift clock frequency. When the DIR pin is high,
CSI/CSO is the input/output for the chip select pulse. When DIR
is low, CSI/CSO is the output/input for the chip select pulse. The
DIR = HIGH also allows the HV623 to shift data in the counter-
clockwise direction when viewed from the top of the package.
When the DIR pin is low, data is shifted in the clockwise direction.

The output circuitry allows the energy which is stored in the output
capacitance to be returned to V

through the body diode of the

output transistor.

Ordering Information

Package Option

Device

64-Lead 3-sided Plastic Gullwing

HV623

HV623PG

12-123

HV623

Symbol

Parameter

Min

Typ

Max

Units

Conditions

AOH

High-voltage analog output source current

See Performance Curves

= 80V

See test circuit

AOL

High-voltage analog output sink current

See Performance Curves

= 80V, V

= 4.5V

= 2V

Maximum delta voltage between high voltage outputs

0.2

At all gray levels

of the same level

Symbol

Parameter

Min

Typ

Max

Units

Conditions

supply current

= 10MHz

= 8MHz

DDQ

Quiescent V

supply current

100

All V

= 0V, V

= max

High-level input current

1.0

= V

Low-level input current

-1.0

-50

= 0V

Input capacitance (data, LC, SC, CC)

= 0V, f = 1MHz

High-level output current

-2

= 4.5V

Low-level output current

= 4.5V

Notes
1. All typical values are at V

= 5.0V.

2. Guaranteed by design.

Electrical Characteristics

(at T

= 25

C, over operating conditions unless otherwise specified)

Low-Voltage DC Characteristics (Digital)

Symbol

Parameter

Min

Typ

Max

Units

Conditions

supply current for bias circuit

Depending on external
bias circuit, see Table 1.

High-Voltage Bias Circuit for Output Variation Control

High-Voltage DC Characteristics

Symbol

Parameter

Min

Typ

Max

Units

Conditions

supply current

100

=10MHz

= 8MHz

DDQ

Quiescent V

supply current

100

All V

= 0V, V

= max

Low-Voltage DC Characteristics (Analog)

Symbol

Parameter

Min

Typ

Max

Units

Low-voltage digital supply voltage

4.5

5.0

5.5

Low-voltage analog supply voltage

4.5

5.0

5.5

High-level input voltage (analog and digital)

-1

Low-level input voltage (analog and digital)

BIAS

control circuit bias voltage

-2

CTL

control circuit control voltage

High-voltage supply

-0.3

Ramp voltage

-2

Shift clock operating frequency (at V

= 5.5V)

10.2

MHz

Operating free-air temperature

-40

Recommended Operating Conditions

Notes:
Power-up sequence should be the following:
1. Connect ground. 2. Apply V

. 3. Set all inputs (Data, CLK, Enable, etc.) to a known state. 4. Apply V

Power-down sequence should be the reverse of the above.

12-124

HV623

Option 1

Option 2

BIAS

CTL

BIAS

CTL

(V)

(

)

(mA)

(V)

(

)

(mA)

0.1

56K

-1.0

56K

1.0

56K

-2.0

56K

5.5

Symbol

Parameter

Min

Typ

Max

Units

Conditions

Shift clock operating frequency

10.2

MHz

DIN

Data-in frequency

20.4

MHz

CSI/CSO pulse to shift clock setup time

CSI/CSO pulse to shift clock hold time

CSI pulse width

Data to shift clock setup time

Data to shift clock hold time

Data-in pulse width

WLC

Load count pulse width

DLCR

Load count to ramp delay

DRCC

Ramp to count clock delay

0.47

DSL

Shift clock to load count delay time

CSC

Shift clock cycle time

WSC

Shift clock pulse width

CCC

Count clock cycle time

WCC

Count clock pulse width

Note 1: Count clock starts counting after 0.47

s min. This is equivalent to a time duration for a linear ramp V

to ramp from 0 to 3V, assuming the minimum value of T

ramp size time of 12

s for V

= 80V.

AC Characteristics

= 5.5V, T

= 25

Logic Timing

Electrical Characteristics

RAMP

Timing

Note 2: The maximum ramp hold time may be longer than 15

s, but the output voltage HV

OUT

will droop due to leakage.

Table 1:

Schemes to control I

bias current, typical I

Symbol

Parameter

Min

Typ

Max

Units

Conditions

Cycle time of ramp signal

Ramp rise time

Ramp hold time

Ramp fall time

TBD

HV623

VCTL

RCTL

VBIAS

12-125

Pin #

Name

Function

30-36

D1-D7

Inputs for binary-format parallel data.

SC (Shift Clock)

Triggers data on both rising and falling edges. This implies that the data rate is always twice the clock
rate (data rate = 20MHz max if clock rate = 10MHz max).

CSI (Chip

Input pin for the chip select pulse (when DIR is high).

Select Input)

Output pin for the chip select pulse (when DIR is low).

CSO (Chip

Input pin for the chip select pulse (when DIR is low).

Select Output)

Output pin for the chip select pulse (when DIR is high).

Input for a pulse whose rising edge causes data from the input latches to enter the comparator latches,

(Load Count)

and whose falling edge initiates the conversion of this binary data to an output level (D-to-A).
Also, the HV

OUT

will clear to zero after the load count is initiated.

CC (Count Clock) Input to the count clock generator whose increments are compared to the data in the comparator latches.

18, 47

High-voltage ramp input for charging the output stage hold capacitors (C

This input can be linear or non-linear as desired.

DIR

When this pin is connected to V

, input data is shifted in ascending order,

i.e., corresponding to HV

OUT

1 to HV

OUT

32. When connected to LVGND, input data is shifted

in descending order, i.e., corresponding to HV

OUT

32 to HV

OUT

27, 38

LVGND

This is ground for the logic section.
HVGND and LVGND should be connected together externally.

17, 48

HVGND

This is ground for the high-voltage (output) section.
HVGND and LVGND should be connected together externally.

19, 45

This input biases the output source followers.

1-16

OUT

High-voltage outputs.

49-64

OUT

(Analog)

Low-voltage analog supply voltage.

(Digital)

Low-voltage digital supply voltage.

CTL

Voltage supply pin to prevent output voltage from being affected by its adjacent outputs (V

CTL

= 2V for a

particular panel). The combination of V

CTL

and R

CTL

will reduce the output voltage variation to less than

0.2V of delta voltage between high voltage outputs of the same level at all gray levels.

CTL

Current sense resistor to ground to prevent output voltage from being affected by its adjacent outputs
(R

CTL

= 56K

for a particular panel). See V

CTL

function above.

Pin Definitions

Input and Output Equivalent Circuits

Input

GND
(Logic)

Logic Inputs

GND
(Logic)

Data Out

Logic Data Output

HV623

12-126

Functional Block Diagram

Output

Stage

Latches and

Comparators

Latches and

Comparators

Latches and

Comparators

Latches and

Comparators

Load

Count

Clear

Dual

16-bit

Shift Registers

GND

OUT

Output

Stage

OUT

Data In
Buffers

OUT

CTL

Output

Stage

Counter

Reset

Counter

OUT

Data

Latches

Data

Latches

Data

Latches

Data

Latches

F/F

L/E

Clear

Pulse

Generator

Load

Count
Buffer

Count

Clock

Buffer

Load

Count

Shift

Clock

Buffer

CSI

I/O

Buffers

DIR

CSO

I/O

Buffers

See Output Stage Detail

Output

Stage

SC = Shift Clock

LC = Load Count

CC = Count Clock

CSI = Chip Select Input

CSO = Chip Select Output

*Strobe = twice the SC frequency

Logic

70V

HV623

Output

Stage

HVGND

LVGND

= 80V

OUT

tst

10K

1. Set HV

OUT

= Low.

2. Apply V

= 80V.

3. Apply a step voltage of 70V at V

(slew rate = 4.1V/

s).

4. Measure voltage across the 1K

resistor.

5. Output source current can be calculated by using

tst

Internal

Logic

Bias

Circuit

CTL

OUT

Test Circuit

High-voltage Analog Output Source Current (I

AOH

)

For gray shade #1 (000 0000)

Output Stage Detail

HV623

12-127

HV623

Gray Scale Voltage

Gray Shade Decoding Scheme

Shade Number

128

127

126

125

124

123

122

121

OUT

1 2

· · ·

127

Gray Scale Voltage

Clock Cycle

(000 0000)

(111 1111)

Typical Panel Connections

, V

LVGND, HVGND,

SC, LC, CC, CSO

, V

LVGND, HVGND,

SC, LC, CC, CSI

Data Bus

(7)

DIR = LOW

DIR = HIGH

Data Bus

(7)

Display Panel

(Example)

12-128

HV623

Sequence

Function

DIR

Data-In

CSI

CSO

Shift

Load

Count

OUT

(D1 - D7)

Clock

Count

Clock

Shift Data

Output

from HV

OUT

1 to 32

Shift Data

Output

from HV

OUT

32 to 1

Load Shift Register

Load Counter

Pre-define by 1 or 2

Counting/Voltage

Initiates

Conversion

RAMP

Function Table

Chip Select

Input (CSI)

Load

First

Device

Load

Second

Device

Load

Last

Device

128

DLCR

Chip Select

Output (CSO)

Shift Clock

(SC)

Load Count*

(LC)

Count Clock

(CC)

OUT

Data from Data Bus (See Detailed Timing)

*HV

OUT

will clear to zero with load count.

128

Data In

(D1 - D7)

Timing Diagrams

(a) Basic System Timing

12-129

HV623

(b) Detailed Device Timing

DATA

SET 1

DATA

SET 2

DATA

SET 3

DATA

SET 31

DATA

SET 32

WLC

DSL

DATA

SET 1

DATA

SET 31

LOADING LAST DEVICE

NEXT LOADING CYCLE

Chip Select

Input (CSI)

Data

(D1-D7)

Shift Clock

(SC)

Load Count

(LC)

Count Clock

(CC)

Count

Clock 1

Count

Clock 128

DLCR

DRCC

80V

CSC

SC 2

SC 16

SC 1

SC 16

WCC

CCC

SC 1

Typical Performance Curves

Sink Output Characteristics

Source Output Characteristics

Volts

(milliamperes)

12-130

HV623

Pin

Function

64-Pin PG Package

Pin

Function

OUT

HVGND

N/C

(Analog)*

CSI

Pin Configuration

Pin

Function

N/C

CTL

SC (Shift Clock)

LVGND

DIR

(Digital)*

N/C

LVGND

N/C

LC (Load Count)

N/C

CC (Count Clock)

CSO

N/C

HVGND

OUT

Package Outlines

* Analog V

and digital V

may be connected

separately for better noise immunity.

3-Sided Plastic QFP 64-pin Gullwing Package

top view

Index

Theory of Operation

The HV623 has two primary functions:

1) Loading data from the data bus and,

2) Gray-shade conversion

(converting latched data to output voltages).

Since the device was developed initially for flat panel displays, the
operation will be described in terms that pertain to that technol-
ogy. As shown by the Typical Drive Scheme, several HV623
packages are mounted at the top and bottom of a display panel.
Data exists on a 7-bit bus (adjacent PC board traces) at top and
bottom. The D1 through D7 inputs of each chip take data from the
bus when either a CSI or CSO pulse is present at the chip. These
pulses therefore act as a combination CHIP SELECT and LOCA-
TION STROBE. Because of the way the chip HV

OUT

pins are

sequenced, data on the bus at the bottom of the display panel will
be entered into the left-most chip as HV

OUT

etc. up to

OUT

32. The CSI pulse will accomplish this with DIR = High.

Loading Data from Data Bus

Here is the full data-entry sequence:

1) The microcontroller puts data on the bus (7 bits)

2) To enter the data into the 32 sets of 7 latches on the first chip,

the shift clock rises. This positive transition is combined with
the CSI pulse and is generated only once to strobe the data into
the first set of latches. (These latches eventually send data to
the HV

OUT

1). The data on the bus then changes, the shift clock

falls, and this negative transition is combined with the CSI
pulse, which is now propagated internally, to strobe the new
data into the next set of 7 latches (which will end up as
HV

OUT

2). This internal CSI pulse therefore runs at twice the

shift clock rate.

3) When the last set of 7 latches in the first chip has been loaded

(HV

OUT

32), the CSI pulse leaves chip 1 and enters chip 2. The

exit pin is called CSO and the chip 2 entry pin is CSI . For chips
at the top of the panel things are reversed: DIR is low, entry pins
are CSO and exit pins are CSI , because the data-into-latches
sequence is in descending order, HV

OUT

32 down to HV

OUT

4) The buses may of course be separate, and data can be strobed

in on an interleaved basis, etc., but those complications will be
left to systems designers.

12-131

HV623

When data has been loaded into all 32 outputs of all chips (top and
bottom of the display panel), the load count pin is pulsed. On its
rising transition, all output levels are reset to zero and all the data
in the input latches is transferred to a like number of comparator
latches, (thus leaving the data latches ready to receive new data
during the following operations). After the transfer, the load count
pin is brought low. This transition begins the events that convert
the binary data into a gray-shade level.

Gray-shade Conversion

1) The COUNT CLOCK is started. An external signal is applied

to the COUNT CLOCK pin, causing the counter on each chip
to increment from binary 000 0000 to 111 1111 (0 to 127).

2) At the same time, the V

voltage is applied to all chips, via

charging transistors, causing the HOLD CAPACITOR (C

) on

each output to experience a rise in voltage.

3) The logic control compares the count in the comparator latch

to the count clock. The gate voltage of Q

and the output

voltage HV

OUT

will ramp up at the same rate as V

4) Once V

has reached the maximum voltage, then all the pixels

will be at the final value. (See Output Gray Scale Voltage.)

Output Voltage Variation

The output voltage of the HV623 is determined by the logic and
the ramp voltage V

. It is possible that the output voltage may be

coupled to an unacceptable level due to its adjacent outputs
through the panel. In order to solve this problem, internal logic
(refer to Output Stage Detail) is integrated in the IC to minimize
the effect.

Two external pins V

CTL

and R

CTL

allow the feasibility to control the

current flowing through Q

. The V

CTL

pin is connected to a voltage

source and the R

CTL

pin is connected to ground through a resistor

(2V and 56K

are used for a particular panel). The internal bias

circuit will drive the resistor to a voltage level that is equal to the
V

CTL

voltage at steady state through an operational amplifier. The

current flowing through Q1 and Q2 will be limited to V

CTRL

This combination of V

CTL

and R

CTL

will reduce the output voltage

variation to less than

0.2V of delta voltage for each gray shade,

independent of its adjacent output voltages.

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