Supertex inc.

1235 Bordeaux Drive, Sunnyvale, CA 94089

Tel: (408) 222-8888

FAX: (408) 222-4895

www.supertex.com

NR040506

HV732

Initial Release

High Speed ±100V 2A

Integrated Ultrasound Pulser

Features

HVCMOS technology for high performance
0 to ±100V output voltage
±2A source and sink current
Built-in damping for RTZ waveform capability
Gate-clamp for quick output amplitude ramping
Up to 40MHz operation frequency
±3ns matched delay times
Second harmonic is less than -40dB
1.8V to 3.3V CMOS logic interface
7x7 thermally-enhanced 44-lead QFN MCM

Application

Medical ultrasound imaging

General Description

The Supertex HV732 is a single, complete, high-voltage,
high-speed, ultrasound transmitter pulser. It is designed for
medical ultrasound imaging applications.

The HV732 has built-in damping for faster RTZ waveform
capability and high voltage MOSFET gate-clamping function
for quick ramping of the output voltage amplitude.

The HV732 consists of a control logic circuit, level translators,
MOSFET gate drive buffers, clamp circuits, and high current,
high voltage MOSFETs as the ultrasound transmitter pulser
output stage.

In the output stage there are two pairs of MOSFETs. Each
pair consists of a P-channel and an N-channel MOSFET.

They are designed to have the same impedance, and can
provide peak currents of over ±2 amps. The built-in MOSFET
gate driver outputs swing 0 to 12V on P

and N

pins. The

P-channel damp output swings 0 to 5V on the DMPO pin.

Typical Application Circuit

Level
Trans.

DAMP

Level
Trans.

+12V

Level
Trans.

+12V

SUB

Substrate, PAD

+5 to 12V

AGND

CLAMP

GND

+1.8 to 3.3V

-5V

on/off

Clamp
Circuit

Bias

OUT

RGND

DMPI

DMPO

GATE

10nF

0 to +100V

0 to -100V

OUT

PAD

RGND

10nF

Buffer

NR040506

HV732

Ordering Information

Device

Package Options

44-Lead QFN

HV732

HV732K6

HV732K6-G

-G indicates package is RoHS compliant (`Green')

Absolute Maximum Ratings

Parameter

Value

, logic supply

-0.5V to +5.5V

, positive gate drive supply

-0.5V to +15V

, positive gate drive supply

-0.5V to +15V

, Negative gate drive supply

-5.5V to +0.5V

-V

, differential high voltage supply

+220V

, high voltage positive supply

-0.5V to +200V

, high voltage negative supply

+0.5V to -200V

Storage temperature

-65°C to 150°C

Thermal enhanced package power
dissipation

1.5W

Symbol

Parameter

Min

Typ

Max

Units

Conditions

Operating Supply Voltages and Current

(Over recommended operating conditions unless otherwise specifi ed: AV

= V

= 12V, V

= 3.3V, V

= -5V, T

= 25°C)

Absolute Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation under these conditions is not implied. Continuous operation
of the device at the absolute rating level may affect device reliability. All voltages are
referenced to device ground.

Power-Up Sequence

and V

SUB

Logic supply

1.8

3.3

3.6

---

Positive analog supply

9.0

12.6

---

Positive drive supply

9.0

12.6

---

High voltage positive supply for HV

OUT

100

---

High voltage negative supply for HV

OUT

-100

---

High voltage negative supply for HV

OUT

-4.75

-5.0

-5.25

---

SUB

High voltage positive supply for to bias
substrate

100

Need to be the most positive supply on the
device

DDQ

current EN = Low

175

290

---

DDEN

current EN = High

1.7

2.8

= N

= Low

DDEN

current at 5MHz PW

7.5

f = 5.0MHz, PW D% = 1.0%
No cap on P

, N

PPQ

current EN = Low

2.0

5.0

= +100V, V

= -100V

PPEN

current EN = High

140

180

= N

= Low, V

= +100V, V

= -100V

NNQ

current EN = Low

-1.0

-3.0

= +100V, V

= -100V

NR040506

HV732

NNEN

current EN = High

-140

-180

= N

= Low, V

= +100V, V

= -100V

LLQ

current EN = Low

1.0

5.0

---

LLEN

current EN = High

= N

= Low

LNQ

current EN = Low

-1.0

-5.0

---

LNEN

current EN = High

-230

-320

= N

= Low

Operating Supply Voltages and Current (cont.)

(Over recommended operating conditions unless otherwise specifi ed: AV

= V

= 12V, V

= 3.3V, V

= -5V, T

= 25°C)

Symbol

Parameter

Min

Typ

Max

Units

Conditions

DC Electrical Characteristics

(Over recommended operating conditions unless otherwise specifi ed: AV

= V

= 12V, V

= 3.3V, V

= -5V, T

= 25°C)

Symbol

Parameter

Min

Typ

Max

Units

Conditions

Output P-Channel MOSFET, TX

OUT

Output saturation current

-2.0

= -10V, V

= -25V

Channel resistance

= -10V, I

= -1.0A

Gate to source resistor

= -100A

Source to gate zener voltage

-13.2

-25

= -2.0A

GSF

Gate zener forward voltage

-0.5

-0.8

---

GS(th)

Gate threshold voltage

-1.0

-2.4

= -1.0mA

ISS

Input capacitance

200

= 0V, V

= -25V, f = 1Mhz

OSS

Output capacitance

Output N-Channel MOSFET, TX

OUT

Output saturation current

2.0

= -10V, V

= -25V

Channel resistance

7.0

= -10V, I

= -1.0A

Gate to source resistor

= -100A

Source to gate zener voltage

13.2

= -2.0A

GSF

Gate zener forward voltage

0.5

0.8

---

GS(th)

Gate threshold voltage

1.0

2.0

= -1.0mA

ISS

Input capacitance

110

= 0V, V

= -25V, f = 1Mhz

OSS

Output capacitance

Symbol

Parameter

Min

Typ

Max

Units

Conditions

Output P-Channel Damp MOSFET, OUT

OUT

Output saturation current

-1.0

= -10V, V

= -25V

Channel resistance

= -10V, I

= -1.0A

Gate to source resistor

100

= -100A

Source to gate zener voltage

-13.2

-25

= -2.0A

GSF

Gate zener forward voltage

0.5

0.8

---

GS(th)

Gate threshold voltage

-1.0

-2.6

= -1.0mA

ISS

Input capacitance

200

= 0V, V

= -25V, f = 1Mhz

OSS

Output capacitance

Symbol

Parameter

Min

Typ

Max

Units

Conditions

NR040506

HV732

Output N-Channel Damp MOSFET, OUT

OUT

Output saturation current

1.0

= 10V, V

= 25V

Channel resistance

= 10V, I

= 0.5A

Source to gate zener voltage

1.0

2.6

= 1.0A

ISS

Input capacitance

110

= 0V, V

= 25V, f = 1Mhz

OSS

Output capacitance

Symbol

Parameter

Min

Typ

Max

Units

Conditions

P-Channel Gate Driver Output, P

SINK

Output sink resistance

PDR

= 100mA

SOURCE

Output source resistance

8.0

PDR

= -100mA

PDR

Peak output sink current

2.0

---

PDR

Peak output source current

-2.0

---

Symbol

Parameter

Min

Typ

Max

Units

Conditions

N-Channel Gate Driver Output, N

SINK

Output sink resistance

8.0

NDR

= 100mA

SOURCE

Output source resistance

9.0

NDR

= -100mA

NDR

Peak output sink current

1.0

---

NDR

Peak output source current

-1.0

---

Symbol

Parameter

Min

Typ

Max

Units

Conditions

P-Channel Gate Driver Output, DMPO

SINK

Output sink resistance

DMPO

= 100mA

SOURCE

Output source resistance

DMPO

= -100mA

DMPO

Peak output sink current

0.3

---

DMPO

Peak output source current

-0.3

---

Symbol

Parameter

Min

Typ

Max

Units

Conditions

P-Channel Gate Clamp MOSFET

OUT

Output saturation current

100

---

Channel resistance

---

OSS

Output capacitance

= 0V, V

= 25V, f = 1Mhz

Symbol

Parameter

Min

Typ

Max

Units

Conditions

N-Channel Gate Clamp MOSFET

OUT

Output saturation current

---

Channel resistance

---

OSS

Output capacitance

= 0V, V

= 25V, f = 1Mhz

Symbol

Parameter

Min

Typ

Max

Units

Conditions

NR040506

HV732

Logic Inputs

irf

Inputs rise and fall time

Logic input edge speed requirement

Input logic high voltage

0.8V

---

Input logic low voltage

0.2V

---

Input logic high current

1.0

---

Input logic low current

-1.0

---

Symbol

Parameter

Min

Typ

Max

Units

Conditions

AC Electrical Characteristics

(Over recommended operating conditions unless otherwise specifi ed: AV

= V

= 12V, V

= 3.3V, V

= -5V, T

= 25°C)

out

Output frequency range

MHz

See test curcuit and timing diagram

Output rise time

See relevant test circuit and timing diagram.
Load = 1.0k/220pF

Output fall time

tdr

Delay time on rise time

tdf

Delay time on fall time

delay

Delay time matching

±3.0

From device to device

HD2

Second harmonic distortion

-40

100 resistor load

jitter

Output jitter

Standard deviation of t

samples (1k)

Enable time

See timing diagram

DMPON(P)

Damp switch on delay (P)

OUT

50 to -15V, 10nF from DMPO to

DMPI. See timing diagram.

DMPOFF(P)

Damp switch off delay (P)

DMPON(N)

Damp switch on delay (N)

OUT

50 to +15V.

See timing diagram.

DMPOFF(N)

Damp switch off delay (N)

CLPON(P)

Clamp switch on delay (P)

430

1000

GATE

75 to 0V, 10nF to P

, V

= +12V.

See timing diagram.

CLPOFF(P)

Clamp switch off delay (P)

490

1000

CLPON(N)

Clamp switch on delay (N)

330

550

GATE

75 to 0V, 10nF to N

, V

= -12V.

See timing diagram.

CLPOFF(N)

Clamp switch off delay (N)

316

500

PWRUP

Device power-up delay

150

200

All power supplies up and stable

Symbol

Parameter

Min

Typ

Max

Units

Conditions

Truth Table

Logic Control Inputs

Gate Drive Output

HV Output

Damp Output

CLAMP

DAMP

DMPO

OUT

OFF

NR040506

HV732

HV732 Test Circuit

Level
Trans.

DAMP

Level
Trans.

+12V

Buffer

Level
Trans.

+12V

Buffer

SUB

+5 to 12V

AGND

CLAMP

GND

+1.8 to 3.3V

-5V

on/off

Clamp
Circuit

Bias

OUT

DMPI

DMPO

GATE

10nF

OUT

LOAD

100

Substrate, PAD

PAD

RGND

HV732 TX Switching Time Test

10nF

0 to +100V

0 to -100V

OUT

-5V

+3.3V

+12V

to Oscilloscope

20MHz
3V

0-P

+100V

220pF

DAMP

SUB

AGND

CLAMP

GND

OUT

RGND

DMPI

DMPO

GATE

RGND

HV732

NR040506

HV732

Pin Description

Pin

Function

Description

DMPO

Output of low voltage drive buffer for P-channel damp, 10nF external cap to pin 34 (DMPI)

GND

Drive power ground

Output of low voltage drive buffer for N-DMOS, 10nF external cap to pin 9 (NGATE)

Positive voltage supply for drive circuitry (+12V)

VDD

Positive voltage supply for drive circuitry (+12V)

SUB

Substrate connection of control / driver die chip (connected to the most positive supply, V

)

RGND

Ground return of damp N-DMOS source

OUT

Output of damp N-DMOS drain (open drain output)

NGATE

Gate input of the high voltage N-DMOS, 10nF external cap from pin 3 (N

)

Negative high voltage power supply (-100V)

Output of the high voltage N-DMOS drain (open drain output)

No connection

Output of the high voltage P-DMOS drain (open drain output)

Positive high voltage power supply (+100V)

PGATE

Gate input of the high voltage P-DMOS, 10nF external cap from pin 31 (P

)

OUT

Damp P-DMOS drain (open drain output)

RGND

Ground return of damp P-DMOS

SUB

Substrate connection of control / driver die chip (connected to the most positive supply, V

Positive voltage supply for drive circuitry (+12V)

Output of low voltage drive buffer for P-DMOS, 10nF external cap to pin 25 (PGATE)

GND

Drive power ground

GND

Drive power ground

DMPI

Connects to damp power P-DMOS gate, 10nF cap to pin 1 (DMPO)

Input logic control of the high voltage P-DMOS pin 18 &19 (TX

, Hi = on, Low = off

Negative low voltage power supply (5V)

Positive analog voltage power supply (+12V)

AGND

Analog signal ground (0V)

SUB

Substrate connection of control / driver chip (connected to the most positive supply)

Control / drive chip power enable Hi = on, Low = off

DAMP

Input of damp control on both pin 26 (OUT

) and pin 8 (OUT

), Hi = on, Low = off

CLAMP

Input of clamp switches on both gates of output P-DMOS and N-DMOS, Hi = on, Low = off

Positive voltage supply of low voltage logic (+1.8V to +5V)

Input logic control of the high voltage N-DMOS pin 15 & 16 (TX

), Hi = on, Low = off

Note: The three thermal slabs on the bottom of the package must be externally connected PAD1 to V

SUB

, PAD2 to TX

, and PAD3 to TX

Supertex inc.

1235 Bordeaux Drive, Sunnyvale, CA 94089

TEL: (408) 222-8888 / FAX: (408) 222-4895

www.supertex.com

Supertex inc.

does not recommend the use of its products in life support applications, and will not knowingly sell its products for use in such applications, unless it receives an adequate

"product liability indemnification insurance agreement". Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of the devices
determined defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest
product specifications, refer to the Supertex website: http//www.supertex.com.

Doc.# DSFP - HV732
NR040506

HV732

44-Lead QFN (K6) Package Outline

(The package drawing(s) in this data sheet may not refl ect the most current specifi cations. For the latest package outline
information go to

http://www.supertex.com/packaging.html

1.77 [.070]
1.57 [.062]TYP

0.36 [.014]
0.26 [.010]

1.77 [.070]
1.57 [.062]TYP

0.53 [.021]
0.48 [.019]

0.28 [.011]
0.23 [.009]

0.45 [.018]
0.35 [.014]

0.38 [.015]
0.28 [.011]

0.51 [.020]
0.41 [.016]

3.35 [.141]

3.37 [.133]

4.40 [.173]
4.20 [.165]

0.74 [.029]
0.69 [.027]

7.13 [.281]
6.87 [.271]

7.13 [.281]

6.87 [.271]

PAD2

PAD3

Note:
1. Dimensions in mm. [Inch]
2. Radius is 0.127mm
3. Three thermal slabs on the bottom of the package
must be externally connected PAD1 to V

SUB

PAD2 to TX

, and PAD3 to TX

0.05 [.002]
0.00 [.000]

1.00 [.039]
0.85 [.033]

(N)

(P)

Top View

PAD1

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