1
10V
450V
<
2%
49%
HV9120P
HV9120NG
HV9120PJ
HV9120X
10V
450V
<
2%
99%
HV9123P
HV9123NG
HV9123PJ
HV9123X
Standard temperature range for all parts is industrial (-40
to +85C).
Ordering Information
High-Voltage Current-Mode PWM Controller
General Description
The Supertex HV9120 and HV9123 are Switch Mode Power
Supply (SMPS) controller subsystems that can start and run
directly from almost any DC input, from a 12V battery to a rectified
and filtered 240V AC line. They contain all the elements required
to build a single-switch converter except for the switch, magnetic
assembly, output rectifier(s) and filter(s).
A unique input circuit allows the 912x to self-start directly from a
high voltage input, and subsequently take the power to operate
from one of the outputs of the converter it is controlling, allowing
very efficient operation while maintaining input-to-output galvanic
isolation limited in voltage only by the insulation system of the
associated magnetic assembly. A
2% internal bandgap refer-
ence, internal operational amplifier, very high speed comparator,
and output buffer allow production of rugged, high performance,
high efficiency power supplies of 50 watts or more, which can still
be over 80% efficient at outputs of 1.0W or less. The wide dynamic
range of the controller system allows designs with extremely wide
line and load variations with much less difficulty and much higher
efficiency than usual. The exceptionally wide input voltage accep-
tance range also allows much better usage of energy stored in
input dropout capacitors than with other PWM ICs. Remote on/off
controls allow either latching or nonlatching remote shutdown.
During shutdown, power required is under 6.0mW.
Features
10 to 450V input acceptance range
<1.3mA supply current
>1.0MHz clock
>20:1 dynamic range @ 500KHz
Low internal noise
Feedback
Max
Accuracy
Duty Cycle
Min
Max
+V
IN
Package Options
16 Pin
16 Pin
20 Pin
DIE
Plastic DIP
SOIC
Plastic PLCC
Absolute Maximum Ratings
Voltages are referenced to -V
IN
+V
IN
Input Voltage
450V
V
DD
Device Supply Voltage
15.5V
Logic Input Voltages
-0.3 to V
DD
+ 0.3V
Linear Input Voltages
-0.3 to V
DD
+ 0.3V
I
IN
Preregulator Input Current (continuous)
2.5mA
T
j
Operating Junction Temperature
150
C
Storage Temperature
-65
C to 150C
Power Dissipation, PDIP
1000mW
Power Dissipation PLCC
1400mW
Power Dissipation SOIC
900mW
Applications
Off-line high frequency power supplies
Universal input power supplies
High density power supplies
Very high efficiency power supplies
Extra wide load range power supplies
For detailed circuit and application information, please refer
to application notes AN-H13 and AN-H21 to AN-H24.
HV9120
HV9123
11/12/01
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
2
HV9120/HV9123
Electrical Characteristics
(Unless otherwise specified, V
DD
= 10V, +V
IN
= 48V, Discharge = -V
IN
= 0V, R
BIAS
= 390K
, R
OSC
= 330K
,T
A
= 25
C.)
Symbol Parameters
Min
Typ
Max
Unit
Conditions
Reference
V
REF
Output Voltage
3.92
4.00
4.08
V
R
L
= 10M
3.84
4.00
4.16
R
L
= 10M
,
T
A
= -55
C to 125C
Z
OUT
Output Impedance
1
15
30
45
K
I
SHORT
Short Circuit Current
125
250
A
V
REF
= -V
IN
V
REF
Change in V
REF
with Temperature
1
0.25
mV/
C
T
A
= -55
C to 125C
Oscillator
f
MAX
Oscillator Frequency
1.0
3.0
MHz
R
OSC
= 0
f
OSC
Initial Accuracy
2
80
100
120
KHz
R
OSC
= 330K
160
200
240
R
OSC
= 150K
V
OSC
Voltage Stability
15
%
9.5V < V
DD
<13.5V
TC
OSC
Temperature Coefficient
1
170
ppm/
C
T
A
= -55
C to 125C
PWM
D
MAX
Maximum Duty Cycle
1
HV9120
49.0
49.4
49.6
%
HV9123
95
97
99
Deadtime
1
HV9123
225
nsec
D
MIN
Minimum Duty Cycle
0
%
Minimum Pulse Width
80
125
nsec
Before Pulse Drops Out
1
Current Limit
V
lim
Maximum Input Signal
1.0
1.2
1.4
V
V
FB
= 0V
t
d
Delay to Output
1
80
150
ns
V
SENSE
= 1.5V, V
COMP
2.0V
Error Amplifier
V
FB
Feedback Voltage
3.92
4.00
4.08
V
V
FB
Shorted to Comp
I
IN
Input Bias Current
25
500
nA
V
FB
= 4.0V
V
OS
Input Offset Voltage
nulled during trim
A
VOL
Open Loop Voltage Gain
1
60
80
dB
GB
Unity Gain Bandwidth
1
1.0
1.3
MHz
Z
OUT
Output Impedance
1
see fig. 1
I
SOURCE
Output Source Current
-1.4
-2.0
mA
V
FB
= 3.4V
I
SINK
Output Sink Current
0.12
0.15
mA
V
FB
= 4.5V
PSRR
Power Supply Rejection
1
see fig. 2
dB
Notes:
1. Guaranteed by design. Not subject to production test.
2. Stray C on OSC IN pin must be
5pF.
3
Electrical Characteristics
(continued)
(Unless otherwise specified, V
DD
= 10V, +V
IN
= 48V, Discharge = -V
IN
= 0V, R
BIAS
= 390K
, R
OSC
= 330K
,T
A
= 25
C.)
Symbol Parameters
Min
Typ
Max
Unit
Conditions
Pre-regulator/Startup
+V
IN
Input Voltage
450
V
I
IN
< 10
A; V
CC
> 9.4V
+I
IN
Input Leakage Current
10
A
V
DD
> 9.4V
V
TH
V
DD
Pre-regulator Turn-off Threshold Voltage
8.0
8.7
9.4
V
I
PREREG
= 10
A
V
LOCK
Undervoltage Lockout
7.0
8.1
8.9
V
Supply
I
DD
Supply Current
0.75
1.3
mA
C
L
< 75pF
I
Q
Quiescent Supply Current
0.55
mA
Shutdown = -V
IN
I
BIAS
Nominal Bias Current
20
A
V
DD
Operating Range
9.0
13.5
V
Shutdown Logic
t
SD
Shutdown Delay
1
50
100
ns
C
L
= 500pF, V
SENSE
= -V
IN
t
SW
Shutdown Pulse Width
1
50
ns
t
RW
RESET Pulse Width
1
50
ns
t
LW
Latching Pulse Width
1
25
ns
Shutdown and reset low
V
IL
Input Low Voltage
2.0
V
V
IH
Input High Voltage
7.0
V
I
IH
Input Current, Input Voltage High
1.0
5.0
A
V
IN
= V
DD
I
IL
Input Current, Input Voltage Low
-25
-35
A
V
IN
= 0V
Output
V
OH
Output High Voltage
V
DD
-0.25
V
I
OUT
= 10mA
V
DD
-0.3
I
OUT
= 10mA,
T
A
= -55
C to 125C
V
OL
Output Low Voltage
0.2
V
I
OUT
= -10mA
0.3
I
OUT
= -10mA,
T
A
= -55
C to 125C
R
OUT
Output Resistance
Pull Up
15
25
I
OUT
=
10mA
Pull Down
8.0
20
Pull Up
20
30
I
OUT
=
10mA,
Pull Down
10
30
T
A
= -55
C to 125C
t
R
Rise Time
1
30
75
ns
C
L
= 500pF
t
F
Fall Time
1
20
75
ns
C
L
= 500pF
Note:
1. Guaranteed by design. Not subject to production test.
HV9120/HV9123
4
Shutdown
Reset
Output
H
H
Normal Operation
H
H
L
Normal Operation, No Change
L
H
Off, Not Latched
L
L
Off, Latched
L
H
L
Off, Latched, No Change
Truth Table
Shutdown Timing Waveforms
Functional Block Diagram
V
DD
50%
0
t
d
Output
Sense
1.5V
0
t
SD
50%
90%
90%
V
DD
Output
0
Shutdown
V
DD
0
t
LW
50%
50%
t
SW
50%
50%
t
RW
Reset
0
V
DD
Shutdown
0
V
DD
50%
t
R
, t
F
10ns
t
F
10ns
t
R
10ns
HV9120/HV9123
+
+
+
REF
GEN
+
+
Modulator
Comparator
OSC
R
S
Q
Current Limit
Comparator
9120
COMP
Discharge
OSC
In
OSC
Out
FB
V
REF
BIAS
V
DD
+V
IN
Pre-regulator/Startup
8.6V
8.1V
Undervoltage
Comparator
S
R
Q
V
DD
Shutdown
Reset
-V
Sense
IN
Output
Error
Amplifier
4V
To
Internal
Circuits
1.2V
Current
Sources
To V
DD
2V
T
Q
9123
5 (6)
6 (8)
4 (5)
12 (16)
13 (17)
1 (3)
7 (9)
16 (20)
11 (14)
15 (19)
14 (18)
10 (12)
9 (11)
8 (10)
Pin number in parentheses are for PLCC package.
5
HV9120/HV9123
PSRR -- Error Amplifier and Reference
1M
10K
100
100K
1K
110
Output Switching Frequency
vs. Oscillator Resistance
1M
100 k
10k
10k
R
OSC
(
)
f (Hz)
OUT
80
70
60
50
40
30
20
10
0
-10
100
1K
10K
Error Amplifier
Open Loop Gain/Phase
R
DISCHARGE
vs. t
OFF
(9123 only)
100K
1M
Gain (dB)
Phase (
C)
180
120
60
0
-60
-120
-180
Frequency (Hz)
10
6
10
5
10
4
10
3
10
2
10
1
.1
Error Amplifier Output Impedance (Z
0
)
0
-10
-20
-30
-40
-50
-60
-70
-80
100k
1M
HV9123
HV9120
Bias Resistance (
)
10
7
10
6
10
5
1
Bias Current (
A)
10
100
V
DD
= 10V
V
DD
= 12V
PSSR (dB)
Frequency (Hz)
Z
O
(
)
R
DISCHARGE
(
)
10
3
10
-1
10
2
t
OFF
(nsec)
10
3
10
4
R
OSC
= 100K
R
OSC
= 10K
R
OSC
= 1K
10
4
10
0
10
5
10
1
10
6
10
2
100
1K
10K
100K
1M
Frequency (Hz)
10M
Typical Performance Curves
Fig. 3
Fig. 1
Fig. 4
Fig. 2
Fig. 5
Fig. 6
6
HV9120/HV9123
Test Circuits
Detailed Description
Preregulator
The preregulator/startup circuit for the HV912x consists of a high-
voltage n-channel depletion-mode DMOS transistor driven by an
error amplifier to form a variable current path between the V
IN
terminal and the V
DD
terminal. Maximum current (about 20 mA)
occurs when V
DD
= 0, with current reducing as V
DD
rises. This path
shuts off altogether when V
DD
rises to somewhere between 7.8
and 9.4V, so that if V
DD
is held at 10 or 12V by an external source
(generally the supply the chip is controlling) no current other than
leakage is drawn through the high voltage transistor. This mini-
mizes dissipation.
An external capacitor between V
DD
and V
SS
is generally required
to store energy used by the chip in the time between shutoff of the
high voltage path and the V
DD
supply's output rising enough to
take over powering the chip. This capacitor should have a value
of 100X or more the
effective gate capacitance of the MOSFET
being driven, i.e.,
C
storage
100 x (gate charge of FET at 10V
10V)
as well as very good high frequency characteristics. Stacked
polyester or ceramic caps work well. Electrolytic capacitors are
generally not suitable.
A common resistor divider string is used to monitor V
DD
for both
the undervoltage lockout circuit and the shutoff circuit of the high
voltage FET. Setting the undervoltage sense point about 0.6V
lower on the string than the FET shutoff point guarantees that the
undervoltage lockout always releases before the FET shuts off.
Bias Circuit
An external bias resistor, connected between the bias pin and V
SS
is required by the HV912x to set currents in a series of current
mirrors used by the analog sections of the chip. Nominal external
bias current requirement is 15 to 20
A, which can be set by a
390K
to 510K resistor if a 10V V
DD
is used, or a 510k
to
680K
resistor if V
DD
will be 12V. A precision resistor is
not
required;
5% is fine.
Clock Oscillator
The clock oscillator of the HV912x consists of a ring of CMOS
inverters, timing capacitors, a capacitor discharge FET, and, in
the 50% maximum duty cycle versions, a frequency dividing flip-
flop. A single external resistor between the OSC In and OSC Out
pins is required to set oscillator frequency (see graph). For the
50% maximum duty cycle versions the Discharge pin is internally
connected to V
SS
(ground). For the 99% duty cycle version,
Discharge can either be connected to V
SS
directly or connected to
V
SS
through a resistor used to set a deadtime.
One difference exists between the Supertex HV912x and competi-
tive 912x's: The oscillator is shut off when a shutoff command is
received. This saves about 150
A of quiescent current, which
aids in the construction of power supplies to meet CCITT speci-
fication I-430, and in other situations where an absolute minimum
of quiescent power dissipation is required.
Reference
The Reference of the HV912x consists of a stable bandgap
reference followed by a buffer amplifier which scales the voltage
up to approximately 4.0V. The scaling resistors of the reference
buffer amplifier are trimmed during manufacture so that the output
of the error amplifier when connected in a gain of 1 configuration
is as close to 4.000V as possible. This nulls out any input offset
of the error amplifier. As a consequence, even though the ob-
served reference voltage of a specific part may not be exactly
4.0V, the feedback voltage required for proper regulation will be.
A
50K resistor is placed internally between the output of the
reference buffer amplifier and the circuitry it feeds (reference
output pin and non-inverting input to the error amplifier). This
allows overriding the internal reference with a low-impedance
voltage source
6.0V. Using an external reference reinstates the
input offset voltage of the error amplifier, and its effect of the exact
value of feedback voltage required. In general, because the
reference voltage of the Supertex HV912x is not noisy, as some
previous examples have been, overriding the reference should
seldom be necessary.
Because the reference of the 912x is a high impedance node, and
usually there will be significant electrical noise near it, a bypass
capacitor between the reference pin and V
SS
is strongly recom-
mended. The reference buffer amplifier is intentionally compen-
sated to be stable with a capacitive load of 0.01 to 0.1
F.
+
Reference
V
1
V
2
60.4K
40.2K
1.0V swept 100Hz 2.2MHz
Tektronix
P6021
(1 turn
secondary)
0.1
F
+10V
(V
DD
)
GND
(V
IN
)
(FB)
NOTE: Set Feedback Voltage so that
V
COMP
= V
DIVIDE
1mV before connecting transformer
Error Amp Z
OUT
+
Reference
V
1
V
2
0.1V swept 10Hz 1MHz
0.1
F
10.0V
4.00V
100K1%
100K1%
PSRR
7
HV9120/HV9123
1
8
4
5
6
7
16
9
15
14
13
12
11
10
1
8
2
3
4
5
6
7
16
9
15
14
13
12
11
10
BIAS
FB
COMP
Reset
Shutdown
V
REF
Discharge
OSC In
Error Amplifier
The error amplifier in the HV912x is a true low-power differential
input operational amplifier intended for around-the-amplifier com-
pensation. It is of mixed CMOS-bipolar construction: A PMOS
input stage is used so the common-mode range includes ground
and the input impedance is very high. This is followed by bipolar
gain stages which provide high gain without the electrical noise of
all-MOS amplifiers. The amplifier is unity-gain stable.
Current Sense Comparators
The HV912x uses a true dual comparator system with indepen-
dent comparators for modulation and current limiting. This allows
the designer greater latitude in compensation design, as there are
no clamps (except ESD protection) on the compensation pin. Like
the error amplifier, the comparators are of low-noise BiCMOS
construction.
Remote Shutdown
The shutdown and reset pins of the HV912x can be used to
perform either latching or non-latching shutdown of a converter as
required. These pins have internal current source pull-ups so they
can be driven from open-drain logic. When not used they should
be left open, or connected to V
DD
.
Output Buffer
The output buffer of the HV912x is of standard CMOS construc-
tion (P-channel pull-up, N-channel pull-down). Thus the body-
drain diodes of the output stage can be used for spike clipping if
necessary, and external Schottky diode clamping of the output is
not required.
Detailed Description
(continued)
+V
IN
NC
NC
Sense
Output
V
IN
V
DD
OSC Out
Pinout
16 Pin SOIC
top view
Note: Pins 2 and 3 are removed
16 Pin Dip Package
top view
BIAS
FB
COMP
Reset
Shutdown
V
REF
Discharge
OSC In
+V
IN
Sense
Output
V
IN
V
DD
OSC Out
19
20
1
2
3
18
17
16
15
14
13
12
11
10
9
4
5
6
7
8
FB
BIAS
NC
NC
+V
IN
NC
Discharge
OSC In
OSC Out
V
DD
NC
Sense
Output
NC
V
IN
COMP
Reset
Shutdown
NC
V
REF
20-pin PJ Package
top view
1235 Bordeaux Drive, Sunnyvale, CA 94089
TEL: (408) 744-0100 FAX: (408) 222-4895
www.supertex.com
11/12/01
2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
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