1
HV9605C
General Description
The Supertex HV9605C is a BiCMOS/DMOS single-output,
current mode, pulse width modulator IC designed to meet the
requirements of ETR-080 for ISDN applications. In a 14 pin
package, it provides all the necessary functions to implement a
single-switch PWM with a minimum of external parts.
Utilizing Supertex's proprietary BiCMOS/DMOS technology, it
requires less than one tenth of the operating power of conventional
bipolar PWM ICs. Dynamic range for regulation is also increased
to approximately 8 times that of similar bipolar parts. It operates
directly from any DC input voltage between 15 and 250 VDC. The
START and STOP input voltage thresholds can be programmed
within the operating input voltage range by means of a resistor
divider, provided +V
IN(START)
> +V
IN(STOP)
. The output stage is
push-pull CMOS, eliminating the need for external clamping
diodes. The clock frequency is set with a single external resistor.
High Voltage Current Mode PWM Controller
Features
BiCMOS/DMOS technology
Current mode control
49% duty cycle operation
Programmable START/STOP capability
15V to 250V input range internal start-up regulator
6.0A standby supply current for +V
IN
<20V
0.9mA operating supply current
5.0V V
DD
supply operation
30KHz to 300KHz internal oscillator
15KHz to 150KHz converter output frequency
1.0MHz low offset error amplifier
1.25V 2% band gap reference
Output driver optimized for under 10W applications
Low driver output impedance with V
DD
= 0V
Fast (90nsec) over current shutdown
All pins are ESD protected
Applications
ISDN network terminations
ISDN terminals
ISDN terminal adapters
Feature phones
SLIC circuits
PBX systems
Modems
Distributed power systems
DC/DC converters
Absolute Maximum Ratings*
+V
IN
, Input Voltage
-0.5V to +250V
Supply Voltage, V
DD
-0.5V to +10V
Operating Temperature Range
-40
C to +85C
Storage Temperature Range
-65
C to +150C
Power Dissipation @ 25
C, SOIC
750mW
Power Dissipation @ 25
C, Plastic DIP
1000mW
*All voltages referenced to GND
Preliminary
14 Pin
14 Pin
Die
Plastic DIP
Narrow Body SOIC
+V
IN
Feedback
Max
Package Options
Min
Max
Accuracy
Duty Cycle
15V
250V
<
1%
49%
HV9605CP
HV9605CNG
HV9605CX
Ordering Information
11/12/01
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
2
Supply
V
DD
Operating range
4.7
8.0
V
I
DD
Supply current
0.9
1.3
mA
OUT open,
f
OUT
= 20KHz to 150KHz,
V
DD
= 5V
Pre-Regulator/Start-Up
+V
IN
Regulator input voltage
15
250
V
+I
IN
Input leakage current
6.0
A
+V
IN
=20V, Start=0V, Stop=0V
+I
IN
Input leakage current
15
A
+V
IN
= 50V, V
DD
= 4.7V
+I
IN
Input leakage current
70
A
+V
IN
= 250V, V
DD
= 4.7V
+I
START
Pre-regulator start-up current
5.0
mA
+V
IN
= 15V,
Start & Stop 10M
to + V
IN
V
DD
Regulator output voltage
4.4
4.5
4.6
V
UVLO
Under voltage lockout threshold
4.1
4.2
4.4
V
V
DD
rising
HYST
Under voltage hysteresis
0.1
0.3
0.4
V
Electrical Characteristics
Symbol
Parameters
Min
Typ
Max
Unit
Conditions
Start/Stop Control
V
START
Start threshold
6.72
7.30
7.88
V
I
START
Start input current
0.05
A
+V
IN
= 18V
I
STOP
Stop input current
0.05
A
+V
IN
= 18V
V
CLAMP
Zener clamp voltage on STOP Pin
15
V
MOSFET Driver Output
V
OUT(HIGH)
Output high voltage
4.85
4.90
V
I
OUT
= 10mA, V
DD
= 5.00V
V
OUT(LOW)
Output low voltage
0.05
0.15
V
I
OUT
= -10mA
t
R
Rise time
30
50
nsec
C
L
= 250pF
t
F
Fall time
20
50
nsec
C
L
= 250pF
Oscillator
150
KHz
R
T
= 91K
f
OUT
Output converter frequency
45
50
55
KHz
R
T
= 357K
31.5
35
38.5
KHz
R
T
= 536K
18
20
22
KHz
R
T
= 1.0M
T
C
Temperature coefficient
100
300
PPM/
C f
OUT
= 50KHz
f/f
Voltage stability
1
3
%
f
OUT
= 50KHz, 4.5V< V
DD
<5.5V
HV9605C
3
Status Output
I
SINK
Output current sinking
5.0
10
mA
V
STATUS
= 2.0V
I
SOURCE
Output current sourcing
5.0
10
15
A
V
STATUS(HIGH)
High output voltage
V
DD
-0.2
V
DD
V
No load
V
STATUS(LOW)
Low output voltage
1.0
2.0
V
Sinking 5mA
0.02
0.04
V
Sinking 100
A
t
R
Rise time
1.0
5.0
msec
4.7nF From Status to GND
Error Amplifier
V
FB
Feedback voltage
1.238
1.250
1.263
V
REF shorted to NI, FB
shorted to Comp, T
A
= 25
C
I
FB
or I
NI
Input bias current
25
200
nA
V
FB
= 3.0V, V
NI
= 2.5V
V
OS
Input offset voltage
5.0
25
mV
V
CM
Common mode input range
0
V
DD
-1
V
A
VOL
Open loop voltage gain
65
90
dB
BW
Unity gain bandwidth
1.0
1.5
MHz
I
SOURCE
Output current sourcing
-2
-1
mA
V
FB
< V
NI
I
SINK
Output current sinking
2
4
mA
V
FB
> V
NI
PSRR
Power supply rejection
50
72
dB
4.5V < V
DD
< 5.5V, f=1KHz
Reference
V
REF
Reference output voltage
1.225
1.250
1.275
V
T
A
= 25
C
V
REF
Load regulation
1.0
5.0
mV
0 < I
REF
< 0.3mA
V
REF
Line regulation
2.0
5.0
mV
4.5V < V
DD
< 5.5V
V
REF
Reference output voltage
1.207
1.250
1.293
V
-40
C < T
A
< 85
C
Long term stability
3.0
mV
T
A
= 125
C, 1000hrs
I
REF(SHORT)
Short circuit current
0.5
1.0
mA
V
REF
= SGND
PWM
D
MAX
Maximum duty cycle
49.0
49.9
%
f
OUT
= 20KHz
D
MIN
Minimum duty cycle
0
%
Minimum pulse width before pulse drop out
80
125
nsec
Current Sensing
V
CS
Usable control current sense range
V
CS
(limit)
V
V
CS (LIMIT)
Current limit threshold
0.6
0.7
0.8
V
t
DELAY
Current limit delay to output
90
120
nsec
V
CS
= 1.5V
Electrical Characteristics
(continued)
Symbol
Parameters
Min
Typ
Max
Unit
Conditions
HV9605C
4
Pin Description
SGND
Common connection for all low level signal and
digital circuits. While SGND and PGND must be
electrically connected together, having separate
common pins enhances the ability of the designer
to prevent coupling of noise into critical circuits.
PGND
This pin provides common return for the high
transient current of the output driver circuits. While
PGND and SGND must be electrically connected,
having a separate connection prevents common
noise created by the high transient currents of the
output driver from being injected into critical circuits.
+V
IN
This is the start-up linear pre-regulator input which
can accept DC input voltages in the range of 15V
to 250V. With START and STOP set to more than
20V, the leakage current on this pin is less than
6.0
A at +V
IN
= 20V.
START
The resistive divider from +V
IN
sets the start voltage.
STOP
The resistive divider from +V
IN
sets the stop voltage.
V
DD
This is the supply pin for the PWM circuits. When
the input voltage to the +V
IN
pin exceeds the start
voltage the input regulator seeks to regulate the
voltage on the capacitor connected to this pin to a
nominal 4.5V.
OUT
This high current push-pull CMOS output is intended
to drive the gate of a power MOSFET. In order to
protect the power MOSFET in high electrical noise
environment, this output appears as low impedance
to PGND when V
DD
is at zero volts.
CS
This is the current sense input to the PWM
comparators. Under normal operation the over
current limit is triggered when the voltage on this
pin is at 0.70V and the loop control operating peak
current may be set to any level below this, typically
in the range of 0.2 to 0.5V.
COMP
The low impedance output of the error amplifier.
FB
The high impedance inverting input of the error
amplifier.
NI
The high impedance non-inverting input of the error
amplifier.
REF
This pin provides a 2% accuracy 1.25V low output
impedance buffered reference which is current
limited to 0.5mAmps and should be bypassed,
REF to SGND, with a 0.1
F ceramic capacitor.
RT
The resistor connected from this pin to SGND sets
the frequency of the internal oscillator by setting
the charging current for the internal timing capacitor.
The oscillator frequency is twice the PWM output
frequency.
STATUS
This output is held low until the +V
IN
voltage reaches
the programmed START voltage. It remains low
until the bootstrap supply to V
DD
forces the voltage
above the internal regulator set point. It is further
held low while the control amplifier output on the
COMP pin is forced to its high limit by a low output
from the converter. Once all these conditions are
satisfied, this output will rise to V
DD
with a time
constant set by the external capacitor indicating
that normal operation has been reached. This
output may be used to control the reset of a
microprocessor.
1
7
6
5
4
3
2
14
13
12
11
10
9
8
14 Pin SOIC/DIP Package
COMP
FB
NI
STATUS
RT
SGND
OUT
+V
IN
STOP
START
REF
V
DD
PGND
CS
Pin Configuration
HV9605C
5
Functional Block Diagram
+
--
-
+
+
--
RT
CLK
CLR
Q
A
C
S
OUT
CS
PGND
SGND
Q
R
D
Q
REF
NI
FB
COMP
Bandgap
Reference
Generator
V
DD
V
DD
V
DD
+V
IN
STOP
START
Clock
Oscillator
MOSFET Driver
PWM Good
Bootstrap Good
V
REF
STATUS
UVLO
C
Start-Up
Regulator
Enable
--
+
C
V
START
H
L
Typical Application Circuit
HV9605C
V
DD
STATUS
OUT
CS
PGND
SGND
COMP
FB
NI
REF
RT
START
STOP
48V INPUT
+V
IN
HV9605C
+
+
+
+
+
-
+
40V
ISOLATED
OUTPUT
-
RESET
+5.0V
REFERENCED
TO INPUT (-)
TERMINAL
TN2124K1
or
TN2524N8
1235 Bordeaux Drive, Sunnyvale, CA 94089
TEL: (408) 744-0100 FAX: (408) 222-4895
www.supertex.com
11/12/01
2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
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