1 07/23/02

HV9906

Initial Release

HV9906 FlexSwitch

(Simple Off-Line/PFC & >9V DC/DC Switcher)

Features

Drive one or hundreds of LEDs including White LEDs

Programmable Current Source (mA to A)

Programmable Voltage Source (Steps Up or Down)

Integrator Lock Loop Technology (IL

)

Built in Soft Start

Allows Discontinuous Feedback

Eliminates Compensation Components

Eliminates Output Averaging Filters

Inherent Dither to Reduce EMI

Eliminates High Voltage Input Electrolytic Capacitor

Smallest and Most Reliable Off-Line Solution

Isolated or Non-Isolated Applications

Can be Operated Directly from Rectified AC Mains

10V to 400V Input Range Internal Regulator

<1.5mA Operating Supply Current

Programmable Feed Forward Regulation

Programmable Feedback Sense Threshold (mV to V)

Integrating Differential Sense Feedback

Seamlessly Change from AC to Battery Operation

Applications

LED driver

Power Factor Correction

Constant Current or Voltage Source

Battery Charger / PWM Housekeeping Supplies

Traffic Lights / Street Lights

Back Lighting of Flat Panel Displays

Advertising Signs

Automotive

General Description

The Supertex HV9906 allows the development of the smallest
possible, most reliable, offline and wide DC/DC conversion range
converters for driving LEDs and other applications. The HV9906
combines internally all the components required to operate directly
from the rectified AC line with a feedback mechanism that
eliminates filters & compensation components, and which can
close the loop with feedback from a discontinuous waveform (eg.
LED current).

The HV9906 is capable of driving multiconverters, which have
been shown to provide the best performance to component count
trade off for wide conversion range applications like offline
converters. Applicable multiconverters include bucking & boosting
topologies, in isolated & non-isolated configurations, as well as
power factor correcting topologies from <1W up to 150W.

Proper choice of external components will allow the programming
of currents from <1mA to several amps and will allow stepping up
or stepping down from the input without the need to change
components. For example, the same HV9906 converter nominally
regulating to 60VDC output may operate from 12VDC, or from
rectified AC input to 265V

RMS

The HV9906 utilizes a programmable inversely proportional fast
feed forward algorithm to calculate output on time and a novel
Integrating Lock Loop (IL

) feedback with programmable threshold

differential sensing. The sensed feedback may be positive or
negative with respect to ground and the signal may be
discontinuous. In some topologies this control method permits the
elimination of the bulky input filter capacitor (a small high voltage
ceramic or film capacitor is required to maintain a high frequency
path). This algorithm when used with certain multiconverters such
as the flyback-buck, with a fixed load, results in near constant
frequency with only a small dither which helps meet FCC
requirements.

Typical Application Circuit

GATE

+Vin

Vdd

AGND

HV9906

56uH

15uH

Optional

12VDC to 400VDC

or
65VAC to 280VAC

100

IRFBC30AF

1uF
to
6.8uF

0.033uF

PGND

0.047uF

D1 D2

D4 D3

MURS160

400V

1N4007

MURS160

100k

900k

300k

Von

LED-1
Row 1

20mA

LED-9
Row 1

LED-1
Row 2

20mA

LED-9
Row 2

LED-10

Row 2

LED-1
Row 3

20mA

LED-10

Row 3

LED-9
Row 3

LED-1
Row 25

20mA

LED-9
Row 25

LED-10

Row 25

Q25

NPN Bipolar Transistor Array or Matched 2N2222

Negative Voltage

Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com

HV9906

Absolute Maximum Ratings*

Input Voltage

-0.3V to +450V

-0.3V to +15V

Pulse Width Control Voltage

-0.3 to +10V

PS & NS Pin Feedback Voltage

-0.3V to +10V

Operating Ambient Temperature Range -40

�

C to +85

�

Operating Junction Temperature Range -40

�

C to +150

�

Storage Temperature Range

-65

�

C to +150

�

Thermal Resistance Junction to Ambient, SOIC

159

�

C/W

Thermal Resistance Junction to Case, SOIC

�

C/W

Thermal Resistance Junction to Ambient, Plastic DIP 110

�

C/W

Thermal Resistance Junction to Case, Plastic DIP 35

�

C/W

*All voltages referenced to AGND and PGND connected together.

Ordering Information

Package Options

8 Pin Plastic DIP

8 Pin SOIC

Dice

HV9906P HV9906LG HV9906X

Electrical Characteristics

(Unless otherwise noted T

= 25

�

Symbol Parameter

Min

Typ

Max

Units

Conditions

Input Regulator/Vdd Supply

Input Voltage

8.5

400

* Typical under UVLO

Input Current

1.5

* Gate pin open and operating at F

MAX

DD(REG)

Internal Regulator Output Voltage

UVLO

Under Voltage Lockout Threshold

8.0

Decaying V

HYST

Under Voltage Lockout Hysteresis

0.50

MOSFET Gate Drive Output

Rise Time

nSec

GATE

= 750pF

Fall Time

nSec

GATE

= 750pF

PWM

P(V

)

Output Pulse Width at V

215

300

nSec

= 5.0V

P(V

)

Output Pulse Width at V

3.35

uSec

= 0.2V

MAX

Maximum Output Pulse Width

17.8

uSec

= 0V

MIN

Minimum Output Frequency

13.5

KHz

MAX

Maximum Output Frequency

250

450

KHz

Current Sense

Positive Sense Pin Voltage

0.9

1.1

* Note: V

and V

are matched

Negative Sense Pin Voltage

0.9

1.1

* Note: V

and V

are matched

Pulse Width Control Feed Forward Voltage

Effective Pulse Width Control Voltage Range

0.2

6.0

The "*" denotes specifications that apply over the full temperature range (-40

�

C to +85

�

2 07/23/02

Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com

HV9906

Pinout

HV9906

+Vin

Vdd

AGND

GATE

Von

PGND

Pin Description

� This pin is the input to the internal linear regulator.

�The voltage applied to this pin by a resistor voltage divider

from +V

controls the on time (pulse width) of the gate output.

� This pin is the output of the internal linear regulator and the

supply pin for the internal circuits. It must be bypassed with a low
ESR capacitor to provide a low impedance path for the gate drive
and be capable of storing sufficient energy so that the voltage does
not decay below the UVLO threshold during the time when the
input voltage is below the minimum required by the regulator.

AGND � This pin is the common connection for analog circuits.

GATE � This pin is the output for driving the gate of an external N-
channel MOSFET.

PGND � This is the common connection for the GATE drive circuit.

NS � This pin is the negative terminal of the differential sense
feedback circuit.

PS � This pin is the positive terminal of the differential sense
feedback circuit.

__________________________________________________________________________________________________________________

Functional Block Diagram

VCO

Delay

High Voltage
Regulator

UVLO
and
POR

Bandgap
Reference

+Vin

Von

Vdd

AGND

GATE

PGND

Reset Pulse

Sample Pulse

Vdd

Vref

Driver

3 07/23/02

Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com

HV9906

Functional Description

The HV9906 consists of the following functional blocks:

High Voltage Regulator

Bandgap

Reference

Under Voltage Lockout and Power On Reset

Voltage Controlled Oscillator

Feed Forward On Time Control

Differential Sense Circuit and Programmable Reference

Integrator

Sample and Hold VCO Control

Gate

Driver

Soft

Start

The following sections provide a detailed explanation of each of
these blocks.

High Voltage Regulator

All internal circuits operate from a nominal 10V V

supply

provided by an onboard linear regulator capable of accepting input
voltages up to 400V. This regulator blocks reverse current flow
from V

to +V

, such as in the case when the input voltage is a

full wave rectified sine wave. Therefore, if a sufficiently large
bypass capacitor (>1

�

F) is connected to V

, the operation of the

circuit can be maintained during the times when the full wave
rectified input voltage is less than the regulated output voltage.
High operating frequency and high input voltage applications will
result in increased power dissipation in the regulator. For these
applications efficiency may be improved by bootstrapping the V

pin if a non-isolated +10V output is available. Supertex's high
voltage technology allows a very low current regulator, rather than
a shunt, to power the IC. This makes it possible to continuously
operate the IC from the AC line, within thermal limits & without
bootstrapping, in certain applications.

Bandgap Reference

As the regulator turns on and the V

voltage rises, a bandgap

reference is activated to establish the regulation point of the
regulator and provide the required references for the internal
circuits. The references are strictly internal and not available at
any pin of the device.

Under Voltage Lockout and Power On Reset

On initial power application the high input voltage (up to 400V)
linear regulator charges the capacitor connected to V

and seeks

to provide a stable supply for the internal circuitry. Under voltage
lockout (UVLO) holds the voltage controlled oscillator (VCO)
disabled until the V

supply rises above a nominal 8.5V and

power on reset (POR) clamps the capacitors in the sample and
hold and integrator circuits low for a short time thereafter, thus
setting the VCO to its lowest frequency state. The UVLO has a
0.5V hysteresis to prevent false triggering due to ripple on V

Voltage Controlled Oscillator

The period of the voltage controlled oscillator (VCO) is determined
by the output of the sample and hold circuit while the feed forward
control from the V

pin provides fast direct control of the oscillator

output on time. For unusual operating circumstance the VCO may
be driven to its maximum frequency and the on time may exceed
the period of the oscillator. This will cause cycle skipping or an
effective reduction in output frequency by an integer factor.

Feed Forward On Time Control

The output signal to the gate driver is controlled by a latch that is
set by the output of the VCO and reset by the feed forward on time
control, thus the voltage applied to the V

pin provides direct and

continuous control of the gate drive on time. The on time is
inversely proportional to the applied voltage and there is an
internally set limit to the maximum on time (17.8

�

S) so that 0V will

not result in an infinite on time. Refer to "Programming On Time"
in the Design Information section.

To operate in discontinuous conduction mode with constant energy
transfer per cycle a resistor divider from the input voltage is
connected to the V

pin, thereby providing fast feed forward input

regulation control. This control loop can easily track a rectified
sine wave of input voltage at 50Hz, 60Hz or 400Hz provided that
the capacitor connected at V

can store sufficient energy to

prevent decay below the UVLO threshold during the time when the
rectified sine wave input voltage at +V

is below 10V. For a 100V

50Hz rectified sine wave a 3.3

�

F capacitor connected to V

sufficient to guarantee stable operation.

For power factor correction applications an input voltage peak
detector or a low pass filter can be used to drive the V

pin. This

will provide an essentially constant on time control voltage
resulting in an energy transfer per oscillator cycle directly
proportional to the input voltage.

Differential Sense Circuit and Programmable Reference

The following simplified equivalent circuit is provided to clarify the
operation and programming of this circuit.

Vdd

+1V

To Sample and Hold
Comparators

20pF

To Most Negative

Sense Node
Relative to +1Volt

To Least Negative

Sense Node
Relative to +1 Volt

This differential sense circuit is typically used to monitor the output
voltage or current of a power converter. The circuit operates by
sourcing current (typically 5

�

A) from both the PS and NS pins

which are regulated at a nominal +1V and the control loop seeks to
maintain a sense node voltage (voltage across a current sense
resistor or the voltage across a resistor divider) that will make the
NS and PS currents equal. Regulation is established when there
is zero current difference in the PS and NS pins. This differential
common mode sense method reduces noise sensitivity and
enables the user to define the magnitude of the sensed voltage
(i.e. +100mV for high efficiency or �2.5V to escape the noise floor)
and thus the effective reference, provided the sensed nodes are at
less than +1V with respect to ground.

4 07/23/02

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5 07/23/02

HV9906

Functional Description -

continued

The voltage difference between the sensed nodes will require the
selection of resistor values in series with the NS and PS pins that
will result in current balance. While balance can be achieved even
if neither sensed node is at ground potential, care must be taken to
assure that the dynamic voltage excursions of the sensed node
within the design operating range (i.e. 50KHz to 250KHz) of the
particular application does not result in common mode current
swings in the PS and NS pins that would result in saturation of the
integrators. Saturation at frequencies below the minimum
operating frequency of the application is permitted* since by design
the circuit will soft start from its lowest frequency.

To regulate on a sense node voltage of +0.5V with respect to
ground connect a 200k

resistor from the NS pin to the ground

end of the sense element and a 100k

resistor from the PS pin to

the +0.5V end of the sense element. Since the voltage drop on the
200k

resistor connected to the NS pin is 1V, a reference current

of 5

�

A is established. To achieve current balance in the PS pin

the sensed node must rise to +0.5V.

For regulating a sense node voltage of �1V with respect to ground
connect a 200k

resistor from the PS pin to the ground end of the

sense element and a 400k

resistor from the NS pin to the �1V

end of the sense element. Since the voltage drop on the 200k

resistor connected to the PS pin is 1V, a reference current of 5

�

is established. To achieve current balance in the NS pin the
sensed node must fall to -1V.

For calculating the required resistor values refer to "Programming
the Sense Inputs" in the Design Information section.

Integrator

The differential output current of the differential sense circuit is fed
to two matched internal 20pF capacitors that make up the
differential integrator circuit. The tolerances of these integrated
capacitors are typically

�

5%, however, since they are matched,

their absolute values only affect the peak voltage of the integrators.
Operating at the lowest frequency results in the highest peak
voltage on the integrators, which will saturate if the peak voltage
on the capacitors exceeds 6V, resulting in a loss of regulation.
This must be taken into consideration when deciding on the value
of the sense currents in the PS and NS pins. The signals at the
sensed nodes may be discontinuous (i.e. controlling the average
output current into LEDs) since the signals are cycle-averaged by
the differential integrator. The differential output of the integrator is
fed to the sample and hold comparators.

*The circuit soft starts from the lowest frequency, therefore it is
very likely that the integrators will saturate during startup. By
design the VCO frequency will be incremented in the event of a
saturated condition, thereby guaranteeing that the circuit will start.

Sample and Hold VCO Control

The cycle-averaged outputs of the differential integrator are
compared by the window comparator of the sample and hold
circuit. If the differential integrator outputs are unequal the sample
and hold circuit increments or decrements the VCO control voltage
by a fixed small step resulting in a shorter or longer subsequent
VCO cycle and thus an increased or decreased frequency. When
the cycle-averaged signals from the differential integrator are
nearly equal (within the hysteresis band of the comparators) the
sample and hold function is halted and the off time is unchanged.
Since the frequency is incremented or decremented in small fixed
steps at the end of each cycle the rate of frequency increase or
decrease is a function of the frequency and thus the oscillator
frequency will change exponentially.

In this manner the Integrator Lock Loop (IL

) feedback controls the

oscillator frequency based on a cycle-averaged sensed value to
maintain output regulation. For certain off-line topologies, the
result is near fixed frequency operation for a fixed load with a
dither of a few KHz which helps in meeting FCC conducted
emission requirements.

Gate Driver

The gate driver buffers the output of the VCO and provides
sufficient gate drive power to achieve rise and fall times below
75nS into a 750pF equivalent MOSFET gate. The under voltage
lockout (UVLO) assures that sufficient voltage is available to drive
the gate of standard or logic level threshold MOSFETs.

Soft Start

On initial power application the UVLO and POR resets the output
latch and sets the VCO to its lowest frequency state, which
represents minimum power transfer per VCO cycle. Thereafter,
the differential sense feedback loop increments the frequency in
small steps, increasing the power transfer rate until output
regulation is achieved, thereby providing the required soft start
function.

Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com

HV9906

Design Information

Programming On Time

The instantaneous voltage applied to the V

pin determines the

gate drive output on time for the VCO cycle. The on time is
inversely proportional to the voltage applied to the V

pin and may

be calculated using the following equation:

( )

085

�

Where the effective control range of V

is limited between 0.2V

and 6V. For V

= 0V P(V

) defaults to a nominal maximum of

17.8

�

Depending on the converter topology and worst case operating
conditions the minimum on time and thus the duty cycle may be
programmed.

Programming the Sense Inputs

The PS and NS sense pins are regulated at +1V and each needs
to be programmed to source the same current at the converter
output regulation set point.

In order to calculate the values of R

and R

PS,

the maximum

sense current, which will avoid integrator saturation, must be
determined. Since by design the circuit will inherently soft start
from its lowest frequency, the designer only needs to establish the
lowest operating frequency (f

MIN

) for the design, which corresponds

to minimum converter output power under closed loop control.
Once this frequency is established the maximum PS pin sense
current I

PS(MAX)

, which occurs during start up when V

PSENSE

NSENSE

, can be calculated using the following equation.

MIN

SAT

MIN

)

MAX

(

�

Where C

MIN

is the minimum value of the integrator capacitors, V

SAT

is the minimum saturation level of the integrators and f

MIN

is the

minimum operating frequency of the converter. Inserting these
values the above equation can be simplified.

MIN

)

MAX

(

)

(

)

(

�

MIN

)

MAX

(

�

For the general case, where at regulation neither sensed node
might be at ground potential, the following equation may be used
to calculate the required R

resistor value where V

PSENSE(MIN)

is the

most negative value that the node will see during starting or normal
operation.

)

MAX

(

)

MIN

(

PSENSE

Once the value of R

has been determined the I

and I

sense

currents at the regulation point can be calculated and the value of
R

can be determined as follows.

PSENSE

NSENSE

Where I

= I

= average current in the NS and PS pins at stable

output regulation, V

NSENSE

is the most negative sensed node

voltage with respect to +1V and V

PSENSE

is the least negative

sensed node voltage with respect +1V. V

NSENSE

and V

PSENSE

must

be less than +1V and V

NSENSE

is always more negative than

PSENSE

Example 1.

For a converter operating at a minimum frequency of 50KHz and
sensing a �1V feedback node voltage with respect to ground, the
resistors connected in series with the PS and NS pins will be
determined as follows.

)

MAX

(

�

To provide a margin of safety let I

PS(MAX)

= 5

�

A. Since in this

configuration the resistor in series with the PS pin is connected to
ground, the sense node voltage V

PSENSE(MIN)

= 0V.

�

200

)

(

)

MAX

(

)

MIN

(

PSENSE

200

PSENSE

�

400

)

(

NSENSE

Example 2.

For a converter operating at a minimum frequency of 100KHz and
sensing a +0.5V feedback node voltage with respect to ground, the
resistors connected in series with the PS and NS pins will be
determined as follows.

)

MAX

(

�

To provide a margin of safety let I

PS(MAX)

= 10

�

A. In this

configuration the most negative value of V

PSENSE(MIN)

occurs during

startup at which time it is 0V.

�

100

)

MAX

(

)

MIN

(

PSENSE

100

)

(

PSENSE

�

200

NSENSE

Protection

The HV9906 used as a current source is inherently protected in the
case of an output short. Over voltage protection is easily
accomplished, in the flyback-buck application for example, with no
more than two diodes. Simple protection for voltage mode
applications, and other topologies is easy to accomplish. Call for
more information.

6 07/23/02

Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com

HV9906

Design Information -

continued

Managing Power Dissipation

The maximum I

current required is the sum of the chip operating

current plus the current required to drive the gate of the external
MOSFET at the maximum operating frequency of the particular
application. Depending on the available data on the MOSFET the
current can be calculated by one of the following methods.

GATE

�

GATE

�

Where f is the maximum operating frequency for the application,
Q

GATE

is the total gate charge, C

GATE

is the effective gate

capacitance and V

GATE

is the maximum gate drive voltage, which is

approximately equal to V

The input regulator supplies all the current and the worst-case total
regulator current may be calculated as follows.

GATE

�

GATE

�

As an example for a particular application where C

GATE

= 750pF

and the maximum operating frequency is f = 200KHz the regulator
input current

750

200

�

If the application is operating in an open-air environment with a
known maximum ambient temperature, then the maximum
allowable input voltage may be calculated using the following
equation.

(max)

�

Where T

is the maximum operating junction temperature, T

is the

maximum ambient temperature, R

is the thermal resistance for

the particular package from junction to ambient and I

is the

required input current.

Using the I

calculated in the previous example in a 50

�

maximum ambient and a plastic DIP package the maximum
allowable input voltage is as follows.

303

110

150

(max)

�

DC or RMS

In the event that this maximum allowable input voltage is less than
what is required by the application, then the following means may
be considered to reduce the dissipation in the regulator.

1. Bootstrapping V

from an output of the converter

2. If the input is DC then a resistor can be added in series

with V

3. If the input is AC then a depletion MOSFET may be added

in series with V

4. Encapsulating the circuit with a high thermal conductivity

material

5. Boostrapping V

from an auxiliary bifilar inductor winding

or from an auxiliary transformer winding.

Bootstrapping V

Forcing V

to a voltage greater than the regulation set point

voltage of the internal regulator (i.e. 13V) will force the regulator to
turn off and all the required operating current will be provided by
the forcing source of power. If this power source is derived from
the output of the converter, possibly by means of a secondary
winding on one of the inductors or an additional winding on a
transformer, then the internal regulator will provide the required
current during startup only. Care must be taken to assure that the
absolute maximum voltage rating of the V

pin is not exceeded.

After initial startup, bootstrapping will reduce the power dissipated,
even at the absolute maximum V

voltage, to an essentially

negligible level (V

DD(max)

x I

=15V x 3mA = 45mW).

Operating from a DC input

For DC applications there is usually some minimum operating
voltage. A resistor may be added in series with +V

which can

reduce the effective input voltage to +V

IN(min)

, thereby transferring

some of the power dissipation to the series resistor.

Using the input current of 3mA previously calculated and assuming
an operating input voltage range (V

) of 100VDC to 250VDC for

the application, the maximum value of the series resistor can be
calculated as follows.

�

100

(min)

series

The maximum power dissipation in the resistor will be

)

(

series

�

and the maximum power dissipation in the HV9906 will be

250

(max)

�

which for an SOIC packaged device will result in junction to
ambient temperature difference of 159

�

C/W x 0.48W = 76.32

�

thereby allowing operation up to an ambient temperature of
73.68

�

C for the absolute maximum junction temperature of 150

�

7 07/23/02

Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com

HV9906

Design Information -

continued

Operating from a full wave rectified AC input

For these applications there is no minimum input voltage, thus
adding a fixed value series resistor is not possible. However, a
dynamic resistor consisting of a depletion MOSFET may be added
as depicted in the following diagram.

+Vin

Von

Vdd

AGND

GATE

PGND

HV9906

DN3145N8

This method limits the +V

voltage to V

+ V

GS(OFF)

of the

depletion MOSFET for all input voltages and in fact raises the
maximum allowable peak input voltage to the breakdown voltage
rating of the depletion MOSFET. The worst-case power
dissipation in the HV9906 is now given by the equation

Power Dissipation HV9906 = (

max

)

OFF

(

)

�

and the dissipation in the depletion MOSFET is given by the
equation

Power Dissipation in MOSFET

)

OFF

(

)

(

�

Which for the previously calculated input current of 3mA, 265V

RMS

input voltage and using the DN3145N8 depletion MOSFET yields
the following results.

Power Dissipation HV9906 = (

)

�

Power Dissipation in MOSFET

)

265

(

�

Power Dissipation in MOSFET

0.76W

Using High Thermal Conductivity Encapsulation

For an encapsulated application the required thermal resistance of
the encapsulating material can be calculated using the following
equation.

(max)

)

(

�

is the required thermal resistance of the encapsulating

material.

T

is the maximum junction temperature.

is the maximum ambient temperature.

is the junction to case thermal resistance of the package.

IN(max)

is the maximum DC or RMS input voltage.

is the input current required at the highest operating frequency.

As an example, consider an application where the input current is
3mA as calculated earlier, operating with a maximum input voltage
of 265V

RMS

in an 85

�

C ambient and an SOIC packaged device will

be used. The thermal resistance of the encapsulating material can
then be calculated as follows.

265

)

265

(

150

�

High Thermal Conductivity Encapsulant

Dice

Printed Circuit Board

8 07/23/02

Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com

9 07/23/02

Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com

HV9906

Application Information

Universal Input Non-Isolated Constant 10mA Average Current LED Lamp Power Supply

GATE

+Vin

Vdd

AGND

HV9906

1mH

220uH

Optional

12VDC to 400VDC

65VAC to 280VAC

1 to 8
LEDs

250

VN2460N8

1uF
to
6.8uF

0.01uF

10mA

PGND

0.1uF

D1 D2

D4 D3

MURS120T3

400V

1N4007

MURS120T3

100k

700k

200k

Von

This circuit provides a constant average current output, which may
be used to power LED lamps. The circuit maintains a constant
average current and the value of C4 capacitor controls the peak-to-
peak ripple, which decreases with increasing capacitor value.

If current ripple is permissible then C4 may be omitted.

Universal Input Non-Isolated Constant 0.5A Average Current LED Lamp Power Supply

GATE

+Vin

Vdd

AGND

HV9906

56uH

15uH

Optional

12VDC to 400VDC
or

65VAC to 280VAC

100

IRFBC30AF

1uF
to

6.8uF

0.033uF

PGND

0.047uF

D1 D2

D4 D3

MURS160

400V

1N4007

MURS160

100k

900k

300k

Von

LED-1

Row 1

20mA

LED-9
Row 1

LED-1

Row 2

20mA

LED-9
Row 2

LED-10
Row 2

LED-1

Row 3

20mA

LED-10
Row 3

LED-9
Row 3

LED-1

Row 25

20mA

LED-9
Row 25

LED-10
Row 25

Q25

NPN Bipolar Transistor Array or Matched 2N2222

Negative Voltage

This circuit provides 0.5A constant average current output to power
249 LEDs , each operating at 20mA to form a large LED lamp or
array. The circuit maintains a constant average current and the
value of C4 capacitor controls the peak-to-peak ripple, which
decreases with increasing capacitor value.

If current ripple is permissible then C4 may be omitted.

10 07/23/02

HV9906

Application Information -

continued

Power Factor Corrected Average Current LED Lamp Power Supply

GATE

+Vin

Vdd

AGND

HV9906

80VAC
to
135VAC

PGND

D1 D2

D4 D3

Von

LED-2

Row 1

LED-5
Row 1

LED-2

Row 2

LED-5
Row 2

LED-2

Row 3

LED-5
Row 3

R10

Negative Voltage

LED-1
Row 1

LED-1
Row 2

LED-1
Row 3

This power factor corrected circuit provides a constant average
current output to power LED lamps.

It is intended to meet the following specifications:

Input Voltage

80VAC to 135VAC

LED String Forward Voltage 20V

Power

Factor

>0.95

THD

<15%

10W

12V (6 cell) Lead-Acid Battery Charger

GATE

+Vin

Vdd

AGND

HV9906

12VDC to 400VDC

or
65VAC to 280VAC

10uF

PGND

0.1uF

D1 D2

D4 D3

MURS120T3

1N4007

MURS120T3

12V
Lead-Acid

Battery

150k

225k

Von

400V

100k

0.5

500

13.3k

This floating battery charger circuit will charge a 6 cell 12V lead-
acid battery to a float voltage of 13.8V and provides a 1A charging
current limit for a severely discharged or shorted battery.

When the discharged battery terminal voltage is at 12V, the
charging current is 130mA. The charging current decreases as the
battery charges and the terminal voltage rises. When the
maximum float voltage of 13.8V is reached the current into the
battery will be essentially zero.

Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com

Электронный компонент: HV9906LG

Document Outline