MD1711

Rev.12 011005

Initial Release

High Speed, Integrated Ultrasound Driver IC

Features

Drives two ultrasound transducer channels

Generates 5-level waveform

Drives 12 high voltage MOSFETs

±2.0A source and sink peak current

Up to 20MHz output frequency

12V/ns slew rate

±3ns matched delay times

Second harmonic is less than -40dB

Two separate gate drive voltages

1.8V to 3.3V CMOS logic interface

Applications

Medical ultrasound imaging

Piezoelectric transducer drivers

Metal flaw detection

Nondestructive evaluation

Sonar Transmitter

General Description

The Supertex MD1711 is an IC for a two-channel, 5-
level, high voltage and high-speed transmitter driver.
It is designed for medical ultrasound imaging
applications but can also be used for metal flaw
detection, nondestructive evaluation, and driving
piezoelectric transducers.

The MD1711 is a two-channel logic controller circuit
with low impedance MOSFET gate drivers. There are
two sets of control logic inputs, one for channel A and
one for Channel B. Each channel consists of three
pairs of MOSFET gate drivers. These drivers are
designed to match the drive requirements of the
Supertex TC6320. The MD1711 drives six TC6320s.
Each pair an N-channel and a P-channel MOSFET.
They are designed to have the same impedance and
can provide peak currents of over 2.0 amps

Typical Application Circuit (1 of 2 Channels)

NR012505

TC6320

+100V

-100V

+50V

-50V

DV DD2

DV DD1

VSS

-10V

+10V

VL L

+3 .3 V

AV S S

14
15

SEL

POSA / POS1A

DGND

AGND

MD1711

(1/2 of I/O)

SU B

AV S S

DGND

OUTPA1

OUTNA1

OUTPA2

OUTNA2

OUTPA3

TNA3

DGND

+5V

+1 0 V

+5 V

+10V

+1 0 V

DGND

+10V

-10V

-1 0 V

Transducer

0.22

µF

Control Logic

& Level

Translator

NEGA / NEG1A

HVEN1A / POS2A

HVEN2A / NEG2A

ClampA

0.1

0.22

0.1

10nF

MD1711

NR012505

Ordering Information

Package Option

48 Lead LQFP

MD1711FG

Absolute Maximum Ratings*

, Logic Supply

-0.5V to +5.5V

1, DV

1, Positive Gate Drive Supply

-0.5V to +15V

2, Positive Gate Drive Supply

-0.5V to +15V

, DV

Negative Gate Drive Supply

-15V to +0.5V

Storage temperature

-65°C to 150°C

Junction temperature

125°C

LQFP Power Dissipation

1.2W

*Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional
operation under these conditions is not implied. Continuous operation of the device at the absolute rating level
may affect device reliability. All voltages are referenced to device ground.

Operating Supply Voltages and Currents

(Over operating conditions unless otherwise specified, AV

1=DV

2=10V, AV

=DV

=-10V, V

=3.3V, T

= 25°C)

Sym Parameter

Min Typ Max

Units

Note

Logic

Supply

+1.8

+3.3

+5.5 V

Positive Drive Bias Supply

+8.0

+10

+12.6

Positive Gate Drive Supply

+4.75

+12.6

Positive Gate Drive Supply

+4.75

+12.6

Negative Gate Drive and
Bias Supply

-12.0 -10 -8.0 V

VLL

Logic Supply Current

2.0

AVDD1

Positive Bias Current

5.0

AVSS

DVSS

Negative Drive and Bias
Supply Current

DVDD1

Positive Drive Current 1

All channel on at 5.0Mhz, No load

DVDD2

Positive Drive Current 2

2 = 5.0V, All channel on at

5.0Mhz, No load

AVDD1Q

AVDD1

quiescent current

2.0

AVSSQ

AVSS

quiescent current

0.75

DVDD1Q

DVDD1

quiescent current

DVDD2Q

DVDD2

quiescent current

VLLQ

Logic Supply Current

1.0

EN = low, All inputs low or high.

Thermal resistance to air

°C/W 1oz. 4-layer 3x4inch PCB

MD1711

NR012505

DC Electrical Characteristics

(Over operating conditions unless otherwise specified, AV

1=DV

2=10V, AV

=DV

=-10V, V

=3.3V, T

= 0 to 70°C)

P-Channel Gate Driver Outputs

Sym Parameter

Min

Typ

Max

Units Conditions

SINK

Output sink resistance

6.0

SINK

=100mA

SOURCE

Output source resistance

6.0

SOURCE

=100mA

SINK

Peak output sink current

2.0

SOURCE

Peak output source current

2.0

N-Channel Gate Driver Outputs

Sym Parameter

Min

Typ

Max

Units Conditions

SINK

Output sink resistance

SINK

=100mA

SOURCE

Output source resistance

SOURCE

=100mA

SINK

Peak output sink current

1.5

SOURCE

Peak output source current

1.5

Logic Inputs

Sym Parameter

Min

Typ

Max

Units Conditions

Input logic high voltage

0.8V

Input logic low voltage

0.2V

Input logic high current

1.0

µA

Input logic low current

-1.0

µA

AC Electrical Characteristics

(Over operating conditions unless otherwise specified, AV

1=DV

2=10V, AV

=DV

=-10V, V

=3.3V, T

= 0 to 70°C)

Sym Parameter

Min Typ Max Units Conditions

OUT

Output frequency range

MHz

Propagation delay when output
is from low to high

No load, See timing diagram

Propagation delay when output
is from high to low

No load, See timing diagram

Output rise time

8.0

1000pF load, see timing diagram

Output fall time

8.0

1000pF load, see timing diagram

Delay time matching

±3.0

No load, From device to device

DLAY

Output jitter

Standard deviation of t

samples (1k)

Output slew rate

V/ns

HD2 2

harmonic distortion

-40

Measured at TC6320 output with
100

Load

Power-Up Sequence

1 AV

, DV

Negative Gate Drive Supply and Substrate Bias

2 V

, AV

1, DV

1 & DV

2 Logic Supply, Positive Gate Drive Supply and Bias

MD1711

NR012505

Truth Table for Channels A and B (For SEL = L)

Logic Control Inputs

1 to V

1 Output

2 to V

2 Output

3 to V

3 Output

SEL EN HVEN1/

POS2

HVEN2/

NEG2

Clamp POS/

POS1

NEG/

NEG1

OUT

P1 HV

OUT

N1 HV

OUT

P2 HV

OUT

N2 HV

OUT

0 0 0

ON ON

0 0 0

ON ON

0 0 0

ON ON

0 0 0

OFF OFF

0 0 1

OFF OFF OFF

0 1 0

OFF

ON ON

0 1 0

OFF

0 1 0

OFF

0 1 0

OFF

OFF OFF OFF OFF

0 1 1

OFF OFF OFF

1 0 0

OFF

ON ON

1 0 0

OFF

1 0 0

OFF OFF

OFF

1 0 0

OFF

OFF OFF

1 0 1

OFF OFF OFF

1 1 0

OFF OFF OFF

1 1 1

OFF OFF OFF

X X X

OFF

MD1711

NR012505

Truth Table for Channels A and B (For SEL = H)

Logic Control Inputs

1 to V

1 Output

2 to V

2 Output

3 to V

3 Output

SEL EN Clamp HVEN1/

POS2

HVEN2/
NEG2

POS/
POS1

NEG/
NEG1

OUT

P1 HV

OUT

N1 HV

OUT

P2 HV

OUT

N2 HV

OUT

P3 HV

OUT

0 0 0

OFF

0 0 0

OFF

0 0 0

OFF

0 0 0

OFF OFF

OFF

0 0 1

OFF

0 0 1

OFF

0 0 1

OFF

0 0 1

OFF ON

OFF

0 1 0

OFF

0 1 0

OFF

0 1 0

OFF

0 1 0

ON OFF

OFF

0 1 1

OFF

0 1 1

OFF

0 1 1

OFF

0 1 1

ON ON

OFF

1 0 0

OFF

1 0 0

OFF

1 0 0

OFF

1 0 0

OFF OFF

1 0 1

OFF

1 0 1

OFF

1 0 1

OFF

1 0 1

OFF ON

1 1 0

OFF

1 1 0

OFF

1 1 0

OFF

1 1 0

ON OFF

1 1 1

OFF

1 1 1

OFF

1 1 1

OFF

1 1 1

ON ON

X X X

OFF

Test Circuit for Channel A

Out-PA 1

Out-NA1

Channel A

Control

Logic and

Level

Translation

POSA / POS1A

NEGA / NEG1A

HVEN1A / POS2A

HVEN2A / NEG2A

AG nd

DGnd

GPA1

GNA 1

GPA2

GNA 2

GPA3

GNA 3

OUT

PA1

OUT

NA1

OUT

PA2

OUT

NA2

OUT

PA3

OUT

NA3

Out-PA 2

Out-NA2

Out-PA 3

Out-NA3

LOAD

100

HVout A

10nF

Clam pA

SEL

+10V

+3.3V

-10V

+100 V

-100V

+50V

-50V

Note: Only one of the two
circuit channels is shown.

1/2 of MD1711

3x TC6320

MD1711

NR012505

POS

/ P

NEG

tr,

from

tf,

fall

time from

1 to 0.9V

tr, rise time from
0.9V

2 to 0.9V

tf, fall

tim

e fr

0.9V

fout

Timing Diagram (EN = H, SEL = ClampA = L)

90%

50%

OUT

90%

10%

MD1711

NR012505

Block Diagram / Typical Application Circuit

10nF

+100V

1 F

-100V

1 F

10nF

+100V

1 F

-100V

1 F

10nF

+100V

1 F

-100V

1 F

10nF

+100V

1 F

-100V

1 F

Supertex
TC6320

SEL

AGND

DGND

POSA / POS1A

ClampA

NEGA / NEG1A

HVEN1A / POS2A

HVEN2A / NEG2A

POSB / POS1B

ClampB

NEGB / NEG1B

HVEN1B / POS2B

HVEN2B / NEG2B

Control
Logic
and
Level
Translate

Supertex

MD1711

Piezoelectric
Transducer A

Piezoelectric
Transducer B

MD1711

NR012505

MD1711: Pin Description

Logic supply voltage.

Supplies analog circuitry portion of the gate driver. Should be at
the same potential as DV

Gate drive supply voltage. Supplies digital circuitry portion of the
gate driver and the main output stage for Out-PA2, Out-NA2, Out-
NA3, Out-PB2, Out-NB2, and Out-NB3. Should be at the same
potential as AV

Gate drive supply voltage. Supplies digital circuitry portion of the
gate driver and the main output stage for Out-PA1, Out-NA1, Out-
PB1, and Out-NB1. Can be at a different potential than DV

Gate drive supply voltage for Out-PA3 and Out-PB3. Supplies
digital circuitry portion and the main output stage. Should be at the
same potential as AV

Negative driver supply for Out-PA3, Out-PB3 and bias circuits.
They are also connected to the IC substrate. They are required to
connect to the most negative potential of voltage supplies.

DGND Digital

Ground.

AGND Analog

Ground.

POSA / POS1A

Logic input control for channel A. When SEL = L, the pin is POSA.
When SEL = H, the pin is POS1A.

NEGA / NEG1A

Logic input control for channel A. When SEL = L, the pin is NEGA.
When SEL = H, the pin is NEG1A.

HVEN1A / POS2A

Logic input control for channel A. When SE L= L, the pin is
HVEN1A. When SEL = H, the pin is POS2A.

HVEN2A / NEG2A

Logic input control for channel A. When SEL = L, the pin is
HVEN2A. When SEL = H, the pin is NEG2A.

CLAMPA

Used with SEL = H. Logic input control for Out-PA3 and Out-NA3.
Connect to ground when SEL = L.

Out-PA1, Out-PA2, Out-PA3

Output P-Channel gate drivers for channel A

Out-NA1, Out-NA2, Out-NA3

Output N-Channel gate drivers for channel A

POSB / POS1B

Logic input control for channel B. When SEL = L, the pin is POSB.
When SEL = H, the pin is POS1B.

NEGB / NEG1B

Logic input control for channel B. When SEL = L, the pin is NEGB.
When SEL = H, the pin is NEG1B.

HVEN1B / POS2B

Logic input control for channel B. When SEL = L, the pin is
HVEN1B. When SEL = H, the pin is POS2B.

HVEN2B / NEG2B

Logic input control for channel B. When SEL = L, the pin is
HVEN2B. When SEL = H, the pin is NEG2B.

CLAMPB

Used with SEL = H. Logic input control for Out-PB3 and Out-NB3.
Connect to ground when SEL = L.

SEL

Logic input select. See truth tables for SEL = L and SEL = H.

Logic input enable control. When EN = L, all P-channel output
drivers are high and all N-channel output drivers are low.

Out-PB1, Out-PB2, Out-PB3

Output P-Channel gate driver for channel B

Out-NB1, Out-NB2, Out-NB3

Output N-Channel gate driver for channel B

MD1711

NR012505

Pin Configuration
48-Lead LQFP

Pin Function

1 POSA/POS1A 25

2 NEGA/NEG1A 26

DGND

3 HVEN1A/POS2A

Out-NB2

4 HVEN2A/NEG2A

5 CLAMPA

Out-NB3

6 AV

1 30

DGND

7 AGND

8 CLAMPB

Out-NA3

9 HVEN2B/NEG2B

10 HVEN1B/POS2B 34 Out-NA2
11 NEGB/NEG1B 35 DGND
12 POSB/POS1B 36 DV

13 SEL

37 Out-NA1

14 AV

N/C

15 AV

Out-PA1

16 DV

17 Out-PB3

41 Out-PA2

DGND

42 DV

19 DV

1 43

DGND

20 Out-PB2

44 Out-PA3

21 DV

2 45

22 Out-PB1

46 V

23 N/C

47 EN

24 Out-NB1

48 AV

48-Lead LQFP

Top view

All dimensions are in millimeters

Doc. No. DSFP-MD1711 NR012505

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MD1711FG

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MD1711FG