Supertex inc.
Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: (408) 222-8888
FAX: (408) 222-4895
www.supertex.com
1
NR031706
MD1813
Initial Release
Features
6ns rise and fall time
2A peak output source/sink current
1.2V to 5V input CMOS compatible
5V to 12V supply voltage operation
Smart Logic threshold
Low jitter design
Quad matched channels
Drives two N and two P-channel MOSFETs
Outputs can swing below ground
Built-in level translator for negative gate bias
User-defi ned damping for return-to-zero applications
Non-inverting gate driver OUT
D
for easy logic
Low inductance quad fl at no-lead package
Thermally-enhanced package
Applications
Ultrasound PN code transmitter
Medical ultrasound imaging
Piezoelectric transducer drivers
Nondestructive evaluation
High speed level translator
High voltage bipolar pulser
General Description
The Supertex MD1813 is a high-speed quad MOSFET driver. It is
designed to drive two N and two P-channel, high voltage, DMOS FETs for
medical ultrasound applications, but may be used in any application that
needs a high output current for a capacitive load. The input stage of the
MD1813 is a high-speed level translator that is able to operate from logic
input signals of 1.2 to 5.0 volt amplitude. An adaptive threshold circuit is
used to set the level translator threshold to the average of the input logic
0 and logic 1 levels. The level translator uses a proprietary circuit, which
provides DC coupling together with high-speed operation.
The output stage of the MD1813 has separate power connections,
enabling the output signal L and H levels to be chosen independently
from the driver supply voltages. As an example, the input logic levels may
be 0V and 1.8V, the control logic may be powered by +5V and 5V, and
the output L and H levels may be varied anywhere over the range of 5V
to +5V. The output stage is capable of peak currents of up to 2 amps,
depending on the supply voltages used and load capacitance. The OE
pin serves a dual purpose. First, its logic H level is used to compute the
threshold voltage level for the channel input level translators. Secondly,
when OE is low, the outputs are disabled, with the A output high and the
B output low. This assists in properly pre-charging the coupling capacitors
that may be used in series in the gate drive circuit of an external PMOS
and NMOS. A built-in level shifter is for PMOS gate negative bias driving.
It enables the user-defi ned damping control to generate return-to-zero
bipolar output pulses. The MD1813 has a non-inverting driver OUT
D
for
easy logic.
Typical Application Circuit
High Speed Quad MOSFET Driver
3.3V CMOS
Logic Inputs
10nF
10nF
10nF
+100V
1 F
OUT
A
OUT
B
-100V
1 F
OUT
C
OUT
D
+10V
0.22 F
V
DD
V
H
+10V
0.47 F
V
SS
V
L
V
NEG
GND
OE
-10V
0.47 F
LT
2K
OUT
G
Supertex
MD1813
Supertex
TC2320
Supertex
TC6320
IN
A
IN
B
IN
C
IN
D
ENAB
PULSE
DAMP
To Piezoelectric
Transducer
16
15
1
5
6
3
7
2
4
8
9
10
12
13
11
14
2
NR031706
MD1813
Note: Thermal pad and pin #4, V
NEG
must be connected externally.
Pin #
Function
Description
1
IN
B
Logic input. Controls OUT
B
when OE is high.
.
2
V
L
Supply voltage for N-channel output stage.
3
GND
Device ground.
4
V
NEG
Supply voltage the auxiliary gate drive.
5
IN
C
Logic input. Controls OUT
C
when OE is high.
6
IN
D
Logic input. Controls OUT
D
when OE is high.
7
V
SS
Supply voltage for low-side analog, level shifter, and gate drive circuit.
8
OUT
D
Output driver.
9
OUT
C
Output driver.
10
OUT
G
Auxiliary output driver.
11
V
H
Supply voltage for P-channel output stage
12
OUT
B
Output driver.
13
OUT
A
Output driver.
14
V
DD
Supply voltage for high-side analog, level shifter, and gate drive circuit.
15
IN
A
Logic input. Controls OUT
A
when OE is high.
16
OE
Output enable logic input.
Device
Package Option
16-lead 4x4x0.9 QFN
MD1813
MD1813K6-G
-G indicates package is RoHS compliant (`Green')
16-Lead QFN (K6) Package
1
9
16
13
4
12
5
8
Top View
MD1813
Pin Description
16-Lead QFN (K6) Pin Confi guration
3
NR031706
MD1813
Absolute Maximum Ratings
Symbol
Parameter
Min
Typ
Max
Units
Conditions
Parameter
Value
V
DD
-V
SS
, Logic Supply Voltage
-0.5V to +13.5V
V
H
, Output High Supply Voltage
V
L
-0.5V to V
DD
+0.5V
V
L
, Output Low Supply Voltage
V
SS
-0.5V to V
H
+0.5V
Vss, Low Side Supply Voltage
-7V to +0.5V
V
NEG
-V
SS
, Negative Supply Voltage
V
SS
-13.5V to V
SS
+0.5V
Logic Input Levels
V
SS
-0.5V to V
SS
+7V
Maximum Junction Temperature
+125C
Storage Temperature
-65C to 150C
Soldering Temperature
235C
Package Power Dissipation
2.2W
V
DD
-V
SS
Logic supply voltage
4.5
-
13
V
---
V
SS
Low side supply voltage
-5.5
-
0
V
---
V
H
Output high supply voltage
V
SS
+2
-
V
DD
V
---
V
L
Output low supply voltage
V
SS
-
V
DD
-2
V
---
V
NEG
Negative supply voltage
-13
-
V
SS
-2
V
May connect to V
SS
if OUT
G
not used
I
DDQ
V
DD
quiescent current
-
0.9
-
mA
---
I
HQ
V
H
quiescent current
-
-
10
A
I
NEGQ
V
NEG
quiescent current
120
-
A
I
DD
V
DD
average current
-
8.0
-
mA
V
H
= V
DD
= 12V, V
SS
= V
LL
= GND = 0V,
V
NEG
= -12V,
One channel on at 5.0Mhz, No load
I
H
V
H
average current
-
22
-
mA
I
NEG
V
NEG
average current
-
1.0
-
mA
V
IH
Input logic voltage high
V
OE
-0.3
-
5.0
V
For logic inputs IN
A
, IN
B
, IN
C
, and IN
D
V
IL
Input logic voltage low
0
-
0.3
V
I
IH
Input logic current high
-
-
1.0
A
I
IL
Input logic current low
-
-
1.0
A
V
IH
OE Input logic voltage high
1.8
-
5.0
V
For logic input OE
V
IL
OE Input logic voltage low
0
-
0.3
V
R
IN
Input logic impedance to GND
12
20
30
K
C
IN
Logic input capacitance
-
5.0
10
pF
---
Absolute Maximum Ratings are those values beyond which damage to the
device may occur. Functional operation under these conditions is not implied.
Continuous operation of the device at the absolute rating level may affect
device reliability. All voltages are referenced to device ground.
DC Electrical Characteristics
(V
H
= V
DD
= 12V, V
L
= V
SS
= GND = 0V, V
NEG
= -12V, V
OE
= 3.3V, T
J
= 25
O
C)
4
NR031706
MD1813
Outputs
(V
H
= V
DD
= 12V, V
L
= V
SS
= GND = 0V, V
NEG
= -12V, V
OE
= 3.3V, T
J
= 25
O
C)
R
SINK
Output sink resistance
-
-
12.5
I
SINK
= 50mA
R
SOURCE
Output source resistance
-
-
12.5
I
SOURCE
= 50mA
I
SINK
Peak output sink current
-
2.0
-
A
---
I
SOURCE
Peak output source current
-
2.0
-
A
---
Symbol
Parameter
Min
Typ
Max
Units
Conditions
Symbol
Parameter
Min
Typ
Max
Units
Conditions
t
irf
Input or OE rise & fall time
-
-
10
ns
Logic input edge speed requirement
t
PLH
Propagation delay when output is
from low to high
-
7.0
-
ns
C
LOAD
= 1000pF, see timing diagram
Input signal rise/fall time 2ns
t
PHL
Propagation delay when output is
from high to low
-
7.0
-
ns
t
POE
Propagation delay OE to output
-
9.0
-
ns
t
PCG
Propagation delay IN
C
to OUT
G
-
28
-
ns
t
r
Output rise time
-
6.0
-
ns
t
f
Output fall time
-
6.0
-
ns
l t
r
- t
f
l
Rise and fall time matching
-
1.0
-
ns
for each channel
l t
PLH
-t
PHL
l
Propagation low to high and high
to low matching
-
1.0
-
ns
t
dm
Propagation delay matching
-
2.0
-
ns
Device to device delay match
Logic Inputs
Output
OE
IN
A
IN
B
OUT
A
OUT
B
H
L
L
V
H
V
H
H
L
H
V
H
V
L
H
H
L
V
L
V
H
H
H
H
V
L
V
L
L
X
X
V
H
V
L
OE*
IN
C
IN
D
OUT
C
OUT
G
OUT
D
**
L
L
V
H
V
SS
V
L
L
H
V
H
V
SS
V
H
H
L
V
L
V
NEG
V
L
H
H
V
L
V
NEG
V
H
Note:
* No control to OUT
G
, OUT
C
, or OUT
D
,
** OUT
D
is non-inverting output
AC Electrical Characteristics
(V
H
= V
DD
= 12V, V
L
= V
SS
= GND = 0V, V
NEG
= -12V, V
OE
= 3.3V, T
J
= 25
O
C)
Logic Truth Table
5
NR031706
MD1813
Application Information
For proper operation of the MD1813, low inductance bypass
capacitors should be used on the various supply pins. The GND
pin should be connected to the logic ground. The IN
A
, IN
B
, IN
C
, IN
D
and OE pins should be connected to a logic source with a swing
of GND to V
CC
, where V
CC
is 1.2 to 5.0 volts. Good trace practices
should be followed corresponding to the desired operating speed.
The internal circuitry of the MD1813 is capable of operating up
to 100MHz, with the primary speed limitation being the loading
effects of the load capacitance. Because of this speed and the
high transient currents that result with capacitive loads, the bypass
capacitors should be as close to the chip pins as possible. Unless
the load specifi cally requires bipolar drive, the V
SS
, and V
L
pins
should have low inductance feed-through connections directly to a
ground plane. If these voltages are not zero, then they need bypass
capacitors in a manner similar to the positive power supplies. The
power connections V
DD
should have a ceramic bypass capacitor to
the ground plane with short leads and decoupling components to
prevent resonance in the power leads.
Output drivers, OUT
A
and OUT
C
, drive the gate of an external P-
channel MOSFET, while output drivers OUT
B
and OUT
D
drive the
gate of an external N-channel MOSFET, and they all swing from
V
H
to V
L
. The auxiliary output drive, OUT
G
, swings from V
SS
to V
NEG
,
and drives the external P-channel MOSFET as negative bias via a
2K series resistor.
The voltages of V
H
and V
L
decide the output signal levels. These
two pins can draw fast transient currents of up to 2A, so they
should be provided with an appropriate bypass capacitor located
next to the chip pins. A ceramic capacitor of up to 1.0F may be
appropriate, with a series ferrite bead to prevent resonance in the
power supply lead coming to the capacitor. Pay particular attention
to minimizing trace lengths, current loop area, and using suffi cient
trace width to reduce inductance. Surface mount components are
highly recommended. Since the output impedance of this driver is
very low, in some cases it may be desirable to add a small series
resistance in series with the output signal to obtain better waveform
transitions at the load terminals. This will of course reduce the
output voltage slew rate at the terminals of a capacitive load.
The OE pin sets the threshold level of logic for inputs (V
OE
+ V
GND
) /
2. When OE is low, OUT
A
is at V
H
. OUT
B
is at V
L
, regardless of the
inputs IN
A
or IN
B
. This pin will not control OUT
C
, OUT
D
, or OUT
G
.
Pay particular attention that parasitic couplings are minimized from
the output to the input signal terminals. The parasitic feedback may
cause oscillations or spurious waveform shapes on the edges of
signal transitions. Since the input operates with signals down to
1.2V, even small coupled voltages may cause problems. Use of
a solid ground plane and good power and signal layout practices
will prevent this problem. Be careful that a circulating ground
return current from a capacitive load cannot react with common
inductance to cause noise voltages in the input logic circuitry. Best
timing performance is obtained for OUT
C
when the voltage of (V
SS
-
V
NEG
) = (V
H
-V
L
).
When input logic is high, output will swing to V
L
, and when input
logic is low, output will swing to V
H
. All inputs must be kept low until
the device is powered up.
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