03/12/02

Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.

Absolute Maximum Ratings

Supply voltage, V

-0.5V to +7.5V

Output Voltage, V

+ 0.5V to -95V

Logic input levels

-0.3V to V

+0.3V

Ground Current

1.5A

Continuous total power dissipation

Plastic

1200mW

Ceramic

1900mW

Operating temperature range

Plastic

-40

C to +85

Ceramic -55

C to +125

Storage temperature range

-65

C to +150

Lead temperature 1.6mm (1/16 inch)
from case for 10 seconds

260

Notes:
1. All voltages are referenced to V

2. Limited by the total power dissipated in the package.
3. For operation above 25

C ambient derate linearly to maximum operating

temperature at 20mW/

C for plastic and at 19mW/

C for ceramic.

HV57009

64-Channel Serial To Parallel Converter

With P-Channel Open Drain Controllable Output Current

General Description

The HV570 is a low-voltage serial to high-voltage parallel con-
verter with P-channel open drain outputs. This device has been
designed for use as a driver for plasma panels.

The device has two parallel 32-bit shift registers, permitting data
rate twice the speed of one (they are clocked together). There
are also 64 latches and control logic to perform the blanking of
the outputs. HV

OUT

1 is connected to the first stage of the first shift

register through the blanking logic. Data is shifted through the
shift registers on the logic low to high transition of the clock. The
DIR pin causes CCW shifting when connected to V

, and CW

shifting when connected to V

. A data output buffer is provided

for cascading devices. This output reflects the current status of
the last bit of the shift register (HV

OUT

64). Operation of the shift

register is not affected by the LE (latch enable), or the BL
(blanking) inputs. Transfer of data from the shift registers to
latches occurs when the LE input is high. The data in the latches
is stored when LE is low.

The HV570 has 64 channels of output constant current sourcing
capability. They are adjustable from 0.1 to 2.0mA through one
external resistor or a current source.

Features

Processed with HVCMOS

technology

5V CMOS Logic

Output voltage up to -85V

Output current source control

16MHz equivalent data rate

Latched data outputs

Forward and reverse shifting options (DIR pin)

Diode to V

allows efficient power recovery

Hi-Rel processing available

Package Options

Device

80-Lead Quad

Ceramic Gullwing

80 Lead Quad

Plastic Gullwing

Die

80 Lead Quad

Ceramic Gullwing

(MIL-Std-833 Processed*)

HV57009

HV57009DG

HV57009PG

HV57009X

RBHV57009DG

* For Hi-Rel process flows, refer to page 5-3 of the Databook.

Ordering Information

Symbol

Parameter

Min

Max

Units

Conditions

supply current

= V

, max

CLK

= 8MHz

High voltage supply current

-10

Outputs off, HV

OUT

= -85V

(total of all outputs)

DDQ

Quiescent V

supply current

100

All inputs = V

, except

+IN = V

= GND

High-level output

Data out

-0.5

= -100

OUT

= -2mA

Low-level output

Data out

+0.5

= 100

High-level logic input current

= V

Low-level logic input current

-1

= 0V

HV output source current

-2

REF

= 2V, R

EXT

= 1K,

see Figures 8a and 8b

-0.1

REF

= 0.1V, R

EXT

= 1K,

see Figure 8a and 8b

HV output source current for I

REF

= 2.0mA

REF

= 2V, R

EXT

= 1K

Electrical Characteristics

DC Characteristics

(All voltages are referenced to V

, V

= 0, TA = 25

Symbol

Parameter

Min

Max

Units

Conditions

CLK

Clock frequency

MHz

Per register

, t

Clock width high or low

Data set-up time before clock rises

Data hold time after clock rises

, t

OFF

Time for latch enable to HV

OUT

500

= 15pF

DHL

Delay time clock to data high to low

= 15pF

DLH

Delay time clock to data low to high

= 15pF

DLE

Delay time clock to LE low to high

WLE

Width of LE pulse

SLE

LE set-up time before clock rises

, t

Maximum allowable clock rise and fall time

100

(10% and 90% points)

AC Characteristics

(Logic signal inputs and Data inputs have t

, t

5ns [10% and 90% points] for measurements)

Notes 1: Current going out of the chip is considered negative.

HV57009

HV57009

Input

Logic Inputs

Data Out

Logic Data Output

Input

To Internal
Circuits

Analog Input

OUT

CTL

High Voltage Output

Symbol

Parameter

Min

Max

Units

Logic supply voltage

4.5

5.5

OUT

HV output off voltage

-85

High-level input voltage

- 1.2V

Low-level input voltage

1.2

CLK

Clock frequency per register

MHz

Operating free-air temperature

Plastic

-40

+85

Ceramic

-55

+125

Note:
Power-up sequence should be the following:

1. Connect ground.
2. Apply V

3. Set all inputs to a known state.

Power-down sequence should be the reverse of the above.

Recommended Operating Conditions

Figure 1: Input and Output Equivalent Circuits

HV57009

OUT

·
·
·

OUT

·
·
·

Latch

Programmable

Current

SR2

SR1

CLK

DIR

+IN

-IN

OUT

I/O

2A D

I/O

2B D

I/O

Inputs

Outputs

Function

Data In

CLK

DIR

Shift Reg

HV Outputs

Data Out

All O/P High

Data Stored in Latches

I/O Relation

I/O

1-2A

I/O

1-2A

I/O

1-2B

I/O

1-2B

Figure 4: Function Table

L....L

H....H

n+1

n-1

OFF

New ON or OFF

Previous ON or OFF

New ON or OFF

Notes:
* = dependent on previous stage's state. See Figure 7 for D

and D

OUT

pin designation for CW and CCW shift.

H = V

(Logic)/V

(HV Outputs)

L = V

Note: Each SR (shift register) provides 32 outputs. SR1 supplies outputs 1 to 32 and SR2 supplies outputs 33 to 64.

Figure 3: Functional Block Diagram

Inversion of

Stored Data

Data Falls Through
(Latches Tansparent)

I/O

1-2B

I/O

1-2B

I/O

1-2A

I/O

1-2A

HV57009

Index

top view

80-pin Gullwing Package

HV 32

HV 2

HV 1

HV 33

HV 63

HV 64

SR1

SR2

OUT

DIR = VDD; CW (HVOUT1

HVOUT64)

DIR = VSS; CCW (HVOUT64

HVOUT1)

Pin

Function

OUT

I/O

N/C

CLK

DIR

-IN

I/O

N/C

+IN

Figure 5: Pin Configurations

80-pin Gullwing Package

Pin

Function

OUT

Figure 6: Package Outline

Figure 7: Shift Register Operation

Notes:
1. Pin designation for DIR = V

2. A 0.1

F capacitor is needed between V

and V

(pin 40) for better output

current stability and to prevent transient cross-coupling between outputs.
See Fig. 8a and 8b.

DIR = V

I/O

DIR = V

I/O

HV57009

OUT

REF

EXT

+IN

-IN

10K

390pF

HV570

Logic

To other

outputs

- +

0.1

REF

OUT

0.1

REF

EXT

+IN

-IN

10K

390pF

HV570

Logic

To other

outputs

- +

Since I

OUT

= I

REF

Therefore, if I

OUT

= 2mA and V

REF

= -5V

EXT

= 2.5K

If I

OUT

= 1mA and R

EXT

= 1K

REF

= -1V.

If R

EXT

>10K

, add series network R

and C

to ground for

stability as shown.

This control method behaves linearly as long as the operational
amplifier is not saturated. However, it requires a negative power
source and needs to provide a current I

REF

= I

OUT

for each HV570

chip being controlled.

If HV

OUT

+1V, the HV

OUT

cascode may no longer operate as a

perfect current source, and the output current will diminish. This
effect depends on the magnitude of the output current.

Given I

OUT

and V

REF

, the R

EXT

can be calculated by using:

EXT

REF

OUT

The intersection of a set of I

OUT

and V

REF

values can be located

in the graph shown below. The value picked for R

EXT

must always

be in the shaded area for linear operation. This control method
has the advantage that V

REF

is positive, and draws only leakage

current. If R

EXT

> 10K, add series network R

and C

to ground

for stability as shown.

Note: Lower reference current I

REF

, results in higher distortion,

, on the output.

*Required if R

EXT

> 10K or R

EXT

is replaced by a constant

current source.

Typical Current
Programming Circuits

Figure 8b: Positive Control

Figure 8a: Negative Control

REF

EXT

I OUT

(mA)

VREF (V)

100

250

500

REXT = 1K

1235 Bordeaux Drive, Sunnyvale, CA 94089

TEL: (408) 744-0100 · FAX: (408) 222-4895

www.supertex.com

03/12/02

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: RBHV57009DG

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: RBHV57009DG