TSL1402R
256
1 LINEAR SENSOR ARRAY WITH HOLD
TAOS041 AUGUST 2002
1
The
LUMENOLOGY
r
Company
t
t
Copyright
E
2002, TAOS Inc.
www.taosinc.com
D
256
1 Sensor-Element Organization
D
400 Dots-Per-Inch (DPI) Sensor Pitch
D
High Linearity and Uniformity
D
Wide Dynamic Range . . . 4000:1 (72 dB)
D
Output Referenced to Ground
D
Low Image Lag . . . 0.5% Typ
D
Operation to 8 MHz
D
Single 3-V to 5-V Supply
D
Rail-to-Rail Output Swing (AO)
D
No External Load Resistor Required
D
Replacement for TSL1402
Description
The TSL1402R linear sensor array consists of two sections of 128 photodiodes each and associated charge
amplifier circuitry, aligned to form a contiguous 256
1 pixel array. The device incorporates a pixel data-hold
function that provides simultaneous integration start and stop times for all pixels. The pixels measure 63.5
m
by 55.5
m, with 63.5-
m center-to-center spacing and 8-
m spacing between pixels. Operation is simplified
by internal logic requiring only a serial-input pulse (SI) and a clock.
The TSL1402R is intended for use in a wide variety of applications including mark and code reading, OCR and
contact imaging, edge detection and positioning, and optical encoding.
Functional Block Diagram (each section pin numbers apply to section 1)
2
3
SI
CLK
128-Bit Shift Register
Q128
Switch Control Logic
Integrator
Reset
_
+
Pixel 1
Pixel
2
Pixel
128
Pixel
3
Sample/Hold/
Output
Analog
Bus
Q3
Q2
Q1
Hold
SO
13
Output
Buffer
Gain
Trim
V
DD
AO
GND
5
4
1
t
t
Texas Advanced Optoelectronic Solutions Inc.
800 Jupiter Road, Suite 205
S
Plano, TX 75074
S
(972) 673-0759
(TOP VIEW)
NC No internal connection
V
DD
1
SI1 2
CLK 3
AO1 4
GND 5
SO2 6
NC 7
14 NC
13 SO1
12 GND
11 NC
10 SI2
9 NC
8 AO2
TSL1402R
256
1 LINEAR SENSOR ARRAY WITH HOLD
TAOS041 AUGUST 2002
2
t
t
Copyright
E
2002, TAOS Inc.
The
LUMENOLOGY
r
Company
www.taosinc.com
Terminal Functions
TERMINAL
DESCRIPTION
NAME
NO.
DESCRIPTION
AO1
4
Analog output of section 1.
AO2
8
Analog output of section 2.
CLK
3
Clock. Clk controls charge transfer, pixel output, and reset.
GND
5,12
Ground (substrate). All voltages are referenced to GND.
NC
7, 9,
11, 14
No internal connection.
SI1
2
Serial input (section 1). SI1 defines the start of the data-out sequence for section 1.
SI2
10
Serial input (section 2). SI2 defines the start of the data-out sequence for section 2.
SO1
13
Serial output (section 1). SO1 provides a signal to drive the SI2 input (in serial connection).
SO2
6
Serial output (section 2). SO2 provides a signal to drive the SI input of another device for
cascading or as an end-of-data indication.
V
DD
1
Supply voltage. Supply voltage for both analog and digital circuitry.
Detailed Description
Device operation (assumes serial connection)
The sensor consists of 256 photodiodes, called pixels, arranged in a linear array. Light energy impinging on a
pixel generates photocurrent, which is then integrated by the active integration circuitry associated with that
pixel.
During the integration period, a sampling capacitor connects to the output of the integrator through an analog
switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity on that pixel
and the integration time.
The output and reset of the integrators is controlled by a 256-bit shift register and reset logic. An output cycle
is initiated by clocking in a logic 1 on SI1. An internal signal, called Hold, is generated from the rising edge of
SI1 and simultaneously transmitted to sections 1 and 2. This causes all 256 sampling capacitors to be
disconnected from their respective integrators and starts an integrator reset period. As the SI pulse is clocked
through the shift register, the charge stored on the sampling capacitors is sequentially connected to a
charge-coupled output amplifier that generates a voltage on analog output AO. Simultaneously, during the first
18 clock cycles, all pixel integrators are reset, and the next integration cycle begins on the 19th clock. On the
128th clock rising edge, the SI pulse is clocked out on the SO1 pin (section 1) and becomes the SI pulse for
section 2 (SI2). The rising edge of the 129th clock cycle terminates the SO1 pulse, and returns the analog output
AO1 of section 1 to high-impedance state. Analog output AO2 now becomes the active output. As in section
2, SO2 is clocked out on the 256th clock pulse. Note that a 257th clock pulse is needed to terminate the SO2
pulse and return AO2 to the high-impedance state.
TSL1402R
256
1 LINEAR SENSOR ARRAY WITH HOLD
TAOS041 AUGUST 2002
3
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LUMENOLOGY
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Company
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Copyright
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2002, TAOS Inc.
www.taosinc.com
AO is an op amp-type output that does not require an external pull-down resistor. This design allows a rail-to-rail
output voltage swing.
With V
DD
= 5 V, the output is nominally 0 V for no light input, 2 V for normal white level, and 4.8 V
for saturation light level.
When the device is not in the output phase, AO is in a high-impedance state.
The voltage developed at analog output (AO) is given by:
V
out
= V
drk
+ (R
e
) (E
e
)(t
int
)
where:
V
out
is the analog output voltage for white condition
V
drk
is the analog output voltage for dark condition
R
e
is the device responsivity for a given wavelength of light given in V/(
J/cm
2
)
E
e
is the incident irradiance in
W/cm
2
t
int
is integration time in seconds
The TSL1402R can be connected in the serial mode, where it takes 256 clocks to read out all pixels, or in the
parallel mode where it takes 128 clocks to read out all pixels (see
APPLICATION INFORMATION and FIgures
9 and 10).
A 0.1
F bypass capacitor should be connected between V
DD
and ground as close as possible to the device.
TSL1402R
256
1 LINEAR SENSOR ARRAY WITH HOLD
TAOS041 AUGUST 2002
4
t
t
Copyright
E
2002, TAOS Inc.
The
LUMENOLOGY
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Company
www.taosinc.com
Absolute Maximum Ratings
Supply voltage range, V
DD
0.3 V to 6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
0.3 V to V
DD
+ 0.3V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0) or (V
I
> V
DD
)
20 mA to 20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
DD
)
25 mA to 25 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high impedance or power-off state, V
O
0.3 V to V
DD
+ 0.3 V
. . .
Continuous output current, I
O
(V
O
= 0 to V
DD
)
25 mA to 25 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
DD
or GND
40 mA to 40 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog output current range, I
O
25 mA to 25 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum light exposure at 638 nm
5 mJ/cm
2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
0
C to 70
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
25
C to 85
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Recommended Operating Conditions (see Figure 1 and Figure 2)
MIN
NOM
MAX
UNIT
Supply voltage, V
DD
3
5
5.5
V
Input voltage, V
I
0
V
DD
V
High-level input voltage, V
IH
2
V
DD
V
Low-level input voltage, V
IL
0
0.8
V
Wavelength of light source,
400
1000
nm
Clock frequency, f
clock
5
8000
kHz
Sensor integration time, Parallel, t
int
0.018
100
ms
Sensor integration time, Serial, t
int
0.034
100
ms
Setup time, serial input, t
su(SI)
20
ns
Hold time, serial input, t
h(SI)
(see Note 1)
0
ns
Operating free-air temperature, T
A
0
70
C
NOTE 1: SI must go low before the rising edge of the next clock pulse.
TSL1402R
256
1 LINEAR SENSOR ARRAY WITH HOLD
TAOS041 AUGUST 2002
5
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LUMENOLOGY
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Company
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2002, TAOS Inc.
www.taosinc.com
Electrical Characteristics at f
clock
= 1 MHz, V
DD
= 5 V, T
A
= 25
C,
p
= 640 nm, t
int
= 5 ms,
R
L
= 330
, E
e
= 11
W/cm
2
(unless otherwise noted) (see Note 2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
out
Analog output voltage (white, average over 256 pixels)
See Note 3
1.6
2
2.4
V
V
drk
Analog output voltage (dark, average over 256 pixels)
E
e
= 0
0
0.1
0.2
V
PRNU
Pixel response nonuniformity
See Note 4
10%
Nonlinearity of analog output voltage
See Note 5
0.4%
Output noise voltage
See Note 6
1
mVrms
R
e
Responsivity
See Note 7
25
35
45
V/
(
J/cm
2
)
V
Analog output saturation voltage
V
DD
= 5 V, R
L
= 330
4.5
4.8
V
V
sat
Analog output saturation voltage
V
DD
= 3 V, R
L
= 330
2.5
2.8
V
SE
Saturation exposure
V
DD
= 5 V, See Note 8
136
nJ/cm
2
SE
Saturation exposure
V
DD
= 3 V, See Note 8
78
nJ/cm
2
DSNU
Dark signal nonuniformity
All pixels, E
e
= 0, See Note 9
0.04
0.12
V
IL
Image lag
See Note 10
0.5%
I
Supply current
V
DD
= 5 V, E
e
= 0
6
9
mA
I
DD
Supply current
V
DD
= 3 V, E
e
= 0
5
8
mA
I
IH
High-level input current
V
I
= V
DD
10
A
I
IL
Low-level input current
V
I
= 0
10
A
C
i
Input capacitance, SI
5
pF
C
i
Input capacitance, CLK
10
pF
NOTES: 2. All measurements made with a 0.1
F capacitor connected between V
DD
and ground.
3. The array is uniformly illuminated with a diffused LED source having a peak wavelength of 640 nm.
4. PRNU is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the
device under test when the array is uniformly illuminated at the white irradiance level. PRNU includes DSNU.
5. Nonlinearity is defined as the maximum deviation from a best-fit straight line over the dark-to-white irradiance levels, as a percent
of analog output voltage (white).
6. RMS noise is the standard deviation of a single-pixel output under constant illumination as observed over a 5-second period.
7. R
e(min)
= [V
out(min)
V
drk(max)
]
(E
e
t
int
)
8. SE(min) = [V
sat(min)
V
drk(min)
]
E
e
t
int
)
[V
out(max)
V
drk(min)
]
9. DSNU is the difference between the maximum and minimum output voltage for all pixels in the absence of illumination.
10. Image lag is a residual signal left in a pixel from a previous exposure. It is defined as a percent of white-level signal remaining after
a pixel is exposed to a white condition followed by a dark condition:
IL
+
V
out (IL)
*
V
drk
V
out (white)
*
V
drk
100
Timing Requirements (see Figure 1 and Figure 2)
MIN
NOM
MAX
UNIT
t
su(SI)
Setup time, serial input (see Note 11)
20
ns
t
h(SI)
Hold time, serial input (see Note 11 and Note 12)
0
ns
t
w
Pulse duration, clock high or low
50
ns
t
r
, t
f
Input transition (rise and fall) time
0
500
ns
NOTES: 11. Input pulses have the following characteristics: t
r
= 6 ns, t
f
= 6 ns.
12. SI must go low before the rising edge of the next clock pulse.
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