73M2910L
Microcontroller
April 2000
DESCRIPTION
The 73M2910L high performance micro-controller is
based on the industry standard 8-bit 8032
implemented in an advanced submicron CMOS
process. The processor has the attributes of the
8032, including instruction cycle time, UART, timers,
interrupts, 256 bytes of on-chip RAM and
programmable I/O. The architecture has been
optimized for low power portable modem or
communication applications by integrating unique
features with the core CPU.
A key feature is a user friendly HDLC Packetizer,
accessed through the special function registers. It
has a serial I/O, hardware support for 16 and 32-bit
CRC, zero insert/delete control, a dedicated interrupt
and a clear channel mode for by-passing the
packetizer.
Other features include additional user programmable
I/O with programmable bank select and chip select
logic, designed to eliminate board level glue logic. It
also includes two general-purpose input ports with
programmable wakeup capability.
For devices that require non-multiplexed address
and data buses, eight latched outputs for the low
byte of the address are available.
(continued)
FEATURES
8032 compatible instruction set
44 MHz Operation from 3.3 to 5.5V
HDLC support logic (Packetizer, 16 and 32
CRC, zero ID)
24 pins for user programmable I/O ports
8 pins programmable chip select logic or I/O
for memory mapped peripheral eliminating
glue logic
3 external interrupt sources (programmable
polarity)
16 dedicated latched address pins
Multiplexed data/address bus
Instruction cycle time identical to 8032
Buffered oscillator (or OSC/2) output pin
1.8432 MHz UART clock available
Bank select circuitry to support up to 128k of
external program memory
Also available in 100-Lead QFP and 100-Pin
PGA packages
BLOCK DIAGRAM
(2:0)
USR 1.0
USR 1.1
USR 1.2
USR 1.3
RXD
TXD
PTXCLK
PTXD
PRXCLK
PRXD
OSCIN
OSCOUT
CLK
OUT1
CLK
OUT2
ALE
A (15:0)
D (7:0)
USR5 (1:0)
CSB (7:0)
USR3 (7:0)
USR2 (7:0)
USR1 (7:0)
SFR BUS
TIME GEN
CPU
MEM I/O CTRL
USR I/O
USR I/O
RAM 256 X 8
HDLC
UART
TIMERS
INTERRUPT
CONTROL
ADD/D
A
T
A
IO
73M2910L
Microcontroller
2
DESCRIPTION
(continued)
The 73M2910L has two extra interrupt sources, an
external interrupt and a HDLC interrupt. The HDLC
interrupt has two registers associated with it; the
HDLC Interrupt Register which is used to determine
the source of the interrupt, and the HDLC Interrupt
Enable Register that enables the source of the
interrupt.
The state of the external interrupts can be read
through a register allowing the interrupt pins to be
used as inputs. The interrupt pins INT0 and INT1
can be either negative edge, positive edge or level
triggered. The INT2 pin is always edge triggered.
Two buffered clock outputs have been added to
support peripheral functions such as UARTs,
modems and other clocked devices. The main
internal processor clock frequency can be divided by
2 for power conservation in functional modes that
only require half the clock speed.
Additional internal special function registers are
used for firmware control over the HDLC Packetizer,
the clocks and the programmable I/O ports.
To accommodate processor peripherals when
operating at higher frequencies, the processor's
timing has been altered to allow more address setup
time for slower peripheral program ROM and
memory mapped peripherals.
For low power applications the 73M2910L supports
two power conservation modes: idle and power-down.
In the power-down state the total current consumption
is less than 10 A at room temperature.
DEVELOPER'S NOTE:
The 73M2910L is also available in a
100-Pin PGA package for system developers. The
PGA package is more convenient and reliable for
development emulation systems than the other
package styles. Emulation systems for the
73M2910L are available through Signum Systems,
11992 Challenger Court, Moorpark, CA 93021
(805) 523-9774.
8032 REFERENCE
This Document will describe the features unique to
the 73M2910L. Please refer to a 8032 Programmer's
Guide, Architectural Overview and Hardware
Description for details on the instruction set, timers,
UART, interrupt control, and memory structure.
73M2910L
Microcontroller
3
REGISTER DESCRIPTION
INTERRUPTS
The core chip provides 8 sources of interrupt; 3 external interrupts, 3 timer interrupts, a serial port interrupt,
and an HDLC interrupt. An external interrupt and an HDLC interrupt are unique to the 73M2910L. They do not
exist in a normal 8032 product. Previously unused bits in the IE and IP registers are now serving functions for
these additional interrupt sources. The interrupt vector addresses are as follows:
SOURCE VECTOR
ADDRESS
INT) (IE0)
003H
TF0 00BH
INT! (IE1)
013H
TF1 01BH
RI + TI
023H
TF2 + EXF2
02BH
INT@ - ADDED INTERRUPT
033H
HDLC - ADDED INTERRUPT
03BH
The external interrupt sources, INT(2:0), come from dedicated input pins. The apparent polarity of these pins
is individually controlled by bits in a special interrupt direction register, IDIR (address A9). The interrupt pins
INT! and INT) can be either edge or level generated interrupts as indicated by bits 1 and 3 in the TCON
Register (address 88). Pin
INT@ is always an edge generated interrupt. A flag is set when a falling transition
(rising if IDIR bit 2 is set) on this pin is detected. This flag is automatically cleared when the interrupt is
processed.
INTERRUPT ENABLE REGISTER (IE) SFR ADDRESS 0A8h
Bit Addressable
Reset State 00h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
EA EX2 ET2 ES ET1 EX1 ET0 EX0
NOTE: Bit 6 differs from the 8032. This is a reserved bit in the 8032 and is used as a mask bit for external
interrupt 2 in the core implementation. When bit 6 is set to a 0, external interrupt 2 is disabled.
The mask bit for the HDLC interrupt source is bit 0 of the HDLC Control Register.
INTERRUPT PRIORITY REGISTER (IP) SFR ADDRESS 0B8h
Bit Addressable
Reset State 00h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PHDLC
PX2 PT2 PS PT1 PX1 PT0 PX0
NOTE: Bit 6 and bit 7 differ from the 8032. These are reserved bits in the 8032 and are used to determine
the priority of external interrupt 2 and the HDLC in the core implementation. When bit 6 is set to a 1,
the interrupt is set to the higher priority level.
73M2910L
Microcontroller
4
INTERRUPTS
(continued)
EXTERNAL INTERRUPT DIRECTION REGISTER (IDIR) SFR ADDRESS 092h
Byte Addressable
Reset State 00h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0 0
INT@ INT! INT) INTD2 INTD1 INTD0
These bits determine the polarity of the corresponding external signals INT(2:0) which will result in an interrupt
and will also allow the user to directly read the logic level at the pads INT(2:0).
BITS (5:3) INT(2:0)
Bits (5:3) are read only bits that reflect the logic value at the corresponding pin. The value is not affected by
bits (2:0).
BITS (2:0) Interrupt Polarity Control
If the bit is set to a 0, a falling edge will trigger the interrupt. If the bit is set to a 1, a rising edge will trigger the
interrupt. Also, if the bit is set to a 1, level generated interrupts will occur when the corresponding pin is high
and the internal pin signal to the timer controls will be inverted.
Bits 6 and 7 will always be read as 0's.
CLOCK CONTROL REGISTER SFR ADDRESS 0DAh
Byte Addressable
Reset State 00h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Activity CLK1
CTRL1
MCLK
CTRL
CLK2EN CLK2
CTRL1
CLK2
CTRL0
CLK1EN CLK1
CTRL0
These bits determine the behavior at the CLK1OUT and CLK2OUT pins and allow the user to divide the main
internal processor clock frequency by two for power conservation.
BIT 7
Bit 7 is an activity bit. It is cleared by a read of this register. If the activity bit is set it will prevent the
73M2910L from entering sleep mode.
BIT 6
When bit 6 = 1, CLK1OUT will be OSC/1.5 if bit 1 is a 1 and bit 0 is 0.
BIT 5
CLOCK OUT
0
OSC
1 OSC/2
BIT 5 Master Clock Control
When bit 5 is set to a 1 the internal processor clock is the oscillator frequency divided by 2. If this bit is a 0, the
processor clock is the same frequency as the oscillator's.
73M2910L
Microcontroller
5
BIT 4 Clock 2 Output Enable
Bit 4 enables the clock at the CLOCK 2 output pin if it is set to a 1. The CLOCK 2 pin output is held to a 0, by
writing this bit to a 0. This will reduce system power if the clock pin is not used or if a power reduction mode is
required.
BITS 3,2 Clock 2 Output Control
These bits determine the oscillator divisor for the CLOCK 2 output pin. They were designed to provide a
1.8432 MHz clock for an external UART given an oscillator frequency of 11.0592 MHz, 22.1184 MHz,
18.432 MHz, or 13.824 MHz.
BIT 3
BIT 2
CLK 2 OUT
OSC FREQUENCY
0 0 OSC/7.5 13.824
MHz
0 1 OSC/6
11.059
MHz
1 0 OSC/12 22.118
MHz
1 1 OSC/10 18.432
MHz
BIT 1 Clock 1 Output Enable
Bit 1 enables the clock at the clock 1 output pin if it is set to a 1. The clock pin output is held to a 0, by writing a
0 to this bit. This will reduce system power if the clock pin is not used or if a power reduction mode is required.
Bit 6 is cleared to a 0 upon a reset.
BIT 0 Clock 1 Output Control
Bit 0 controls the frequency of the clock 1 output pin. The clock output is either the oscillator's output signal
divided by two or a buffered oscillator output signal.
POWER SAVING MODES
Low Power Modes
The 73M2910L supports two power conservation modes, which are controlled by the PCON.1 and PCON.0
control bits of the PCON Register.
If PCON.0 is set, the 73M2910L will go into a power saving mode where the oscillator is running, clocks are
supplied to the UART, timers, HDLC, and interrupt blocks, but no clocks are supplied to the CPU. Instruction
processing and activity on the address and data ports is halted. Normal operation is resumed when an
unmasked interrupt is requested or when a reset occurs.
If PCON.1 is set, the 73M2910L goes into its lowest power mode where the oscillator is halted. The total current
consumption in this state should be less than 10 a. The 73M2910L will start its oscillator and begin to return to
normal operation when either a reset occurs, when a falling (rising if corresponding direction bit is set) edge of
an unmasked external interrupt from pins INT(2:0) is detected, or when the USR5 (1:0) pins change to a state
according to the USR5 port register. Edges used in wakeup modes are not filtered in the
73M2910L, so the user must be cautious of noise or small glitches inadvertently waking up the chip. From the
time the edge that results in the wake up occurs, to the point at which an instruction is executed, depends on
the oscillator start-up time. Three good oscillator pulses must be detected before the main internal clocks are
generated.
During power-down mode, both the ALE and PSEN pins are pulled high since these signals often provide the
output enable and chip enable for the ROM (active low). This ensures that the external components are in their
lowest power state.
PDF 
ZIP