Document Outline
- Return to Contents
- List of Figures
- 1. Standard Circuit
- 2. Powering the TC7129 From a 5V Power Supply
- 3. Powering the TC7129 From a Low-Voltage Battery
- 4. Powering the TC7129 From a +5V Power Supply
- 5. External Logic Referenced Directly to DGND
- 6. External Logic Referenced to DGND With Buffer
- 7. Temperature Compensating Circuits
- 8. Oscillator Circuits
- 9. Dual-Slope Conversion
- 10. Accuracy Errors in Dual-Slope Conversion
- 11. Integrator Waveform
- 12. Functional Block Diagram
- 13. Integrator Block Diagram
- 14. Continuity Indicator Circuit
- 15. Input/Output Pin Schematic
- 16. Digital Ground (DGND) and Common Outputs
- 17. Display Segment Assignments
- 18. Backplane Waveforms
- 19. Typical Display Output Waveforms
- List of Tables
- Features
- Ordering Information
- Typical Operating Circuit
- General Description
- Absolute Maximum Ratings*
- Electrical Characteristics
- Electrical Characteristics
- Pin Configurations
- Pin Descriptions
- Pin Descriptions
- Component Selection
- Oscillator
- Integrating Resistor
- Integrating Capacitor
- Reference Capacitor
- Voltage Reference
- Input filter
- Battery
- Special Applications
- The TC7129 as a Replacement Part
- Powering the TC7129
- 5V Power Supply
- Low-Voltage Battery Source
- +5V Power Supply
- Connecting to External Logic
- Temperature Compensation
- RC Oscillator
- Measuring Techniques
- Dual-Slope Conversion
- Successive Integration
- Digital Auto-Zeroing
- Inside the TC7129
- Integrator Section
- Continuity Indicator
- Common and Digital Ground
- Low Battery
- Sequence and Results Counter
- Overrange and Underrange Outputs
- Latch/Hold
- Display Driver
3-231
TELCOM SEMICONDUCTOR, INC.
7
6
5
4
3
1
2
8
TC7129
FEATURES
s
Count Resolution .........................................
19,999
s
Resolution on 200 mV Scale .......................... 10
V
s
True Differential Input and Reference
s
Low Power Consumption ................... 500
A at 9V
s
Direct LCD Driver for 4-1/2 Digits, Decimal Points,
Low-Battery Indicator, and Continuity Indicator
s
Overrange and Underrange Outputs
s
Range Select Input ............................................ 10:1
s
High Common-Mode Rejection Ratio ......... 110 dB
s
External Phase Compensation Not Required
GENERAL DESCRIPTION
The TC7129 is a 4-1/2 digit analog-to-digital converter
(ADC) that directly drives a multiplexed liquid crystal dis-
play (LCD). Fabricated in high-performance, low-power
CMOS, the TC7129 ADC is designed specifically for high-
resolution, battery-powered digital multimeter applications.
The traditional dual-slope method of A/D conversion has
been enhanced with a successive integration technique to
produce readings accurate to better than 0.005% of full
scale, and resolution down to 10
V per count.
The TC7129 includes features important to multimeter
applications. It detects and indicates low-battery condition.
A continuity output drives an annunciator on the display, and
can be used with an external driver to sound an audible
alarm. Overrange and underrange outputs and a range-
change input provide the ability to create auto-ranging
instruments. For snapshot readings, the TC7129 includes a
latch-and-hold input to freeze the present reading. This
combination of features makes the TC7129 the ideal
choice for full-featured multimeter and digital measurement
applications.
TYPICAL OPERATING CIRCUIT
4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER
WITH ON-CHIP LCD DRIVERS
TC7129-5 10/18/96
ORDERING INFORMATION
Pin
Temperature
Part No.
Layout
Package
Range
TC7129CKW Formed
44-Pin PQFP
0
C to +70
C
TC7129CLW --
44-Pin PLCC
0
C to +70
C
TC7129CPL Normal
40-Pin PDIP
0
C to +70
C
TC7129
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
9V
+
TC04
LOW BATTERY CONTINUITY
V+
5 pF
120 kHz
10 pF
0.1
F
20
k
0.1
F
100 k
1
F
0.1
F
150 k
10 k
V+
VIN
+
+
*
NOTE: RC network between pins 26 and 28 is not required.
*
330 k
3-232
TELCOM SEMICONDUCTOR, INC.
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage (V
+
to V
) ............................................ 15V
Reference Voltage (REF HI or REF LO) .............. V
+
to V
Input Voltage (IN HI or IN LO) (Note 1) ................ V
+
to V
V
DISP
................................................ V
+
to (DGND 0.3V)
Digital Input, Pins
1, 2, 19, 20, 21, 22, 27, 37, 39, 40 .......... DGND to V
+
Analog Input, Pins 25, 29, 30 ............................... V
+
to V
Package Power Dissipation (T
A
70
C)
Plastic DIP ........................................................ 1.23W
PLCC ................................................................1.23W
Plastic QFP ....................................................... 1.00W
Operating Temperature Range .................... 0
C to +70
C
Notes: Input voltages may exceed supply voltages, provided input current
is limited to
400
A. Currents above this value may result in invalid display
readings but will not destroy the device if limited to
1 mA.
Dissipation ratings assume device is mounted with all leads soldered to
printed circuit board.
*Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those
indicated in the operational sections of the specifications is not implied.
Exposure to Absolute Maximum Rating Conditions for extended periods
may affect device reliability.
ELECTRICAL CHARACTERISTICS:
V
+
to V
= 9V, V
REF
= 1V, T
A
= +25
C, f
CLK
= 120 kHz, unless otherwise
indicated. Pin numbers refer to 40-pin DIP.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
Input
Zero Input Reading
V
IN
= 0V, 200 mV Scale
0000
0000
+0000 Counts
Zero Reading Drift
V
IN
= 0V, 0
C < T
A
< +70
C
--
0.5
--
V/
C
Ratiometric Reading
V
IN
= V
REF
= 1000 mV, Range = 2V
9997
9999
10000 Counts
Range Change Accuracy
V
IN
= 0.1V on Low Range
0.9999 1.0000
1.0001 Ratio
V
IN
= 1V on High Range
RE
Roll-Over Error
V
IN
= +V
IN
= 199 mV
--
1
2
Counts
NL
Linearity Error
200 mV Scale
--
1
--
Counts
CMRR
Common-Mode Rejection Ratio
V
CM
= 1V, V
IN
= 0V, 200 mV Scale
--
110
--
dB
CMVR
Common-Mode Voltage Range
V
IN
= 0V
--
(V
) +1.5
--
V
200 mV Scale
--
(V
+
) 1
--
V
e
N
Noise (Peak-to-Peak Value Not
V
IN
= 0V
--
14
--
V
P-P
Exceeded 95% of Time)
200 mV Scale
I
IN
Input Leakage Current
V
IN
= 0V, Pins 32, 33
--
1
10
pA
Scale Factor Temperature
V
IN
= 199 mV, 0
C < T
A
< +70
C
--
2
7
ppm/
C
Coefficient
External V
REF
= 0 ppm/
C
Power
V
COM
Common Voltage
V
+
to Pin 28
2.8
3.2
3.5
V
Common Sink Current
Common = +0.1V
--
0.6
--
mA
Common Source Current
Common = 0.1V
--
10
--
A
DGND
Digital Ground Voltage
V
+
to Pin 36, V
+
to V
= 9V
4.5
5.3
5.8
V
Sink Current
DGND = +0.5V
--
1.2
--
mA
Supply Voltage Range
V
+
to V
6
9
12
V
I
S
Supply Current Excluding Common Current
V
+
to V
= 9V
--
0.8
1.3
mA
f
CLK
Clock Frequency
--
120
360
kHz
V
DISP
Resistance
V
DISP
to V
+
--
50
--
k
Low-Battery Flag Activation Voltage
V
+
to V
6.3
7.2
7.7
V
Digital
Continuity Comparator
V
OUT
Pin 27 = High
100
200
--
mV
Threshold Voltages
V
OUT
Pin 27 = Low
--
200
400
mV
Pull-Down Current
Pins 37, 38, 39
--
2
10
A
Storage Temperature Range ................ 65
C to +150
C
Lead Temperature (Soldering, 10 sec) ................. +300
C
TC7129
4-1/2 DIGIT ANALOG-TO-DIGITAL
CONVERTER WITH ON-CHIP LCD DRIVERS
3-233
TELCOM SEMICONDUCTOR, INC.
7
6
5
4
3
1
2
8
33
34
35
36
37
38
39
13
10
9
8
7
18
19
20
21
23
24
6
5
4
3
1
44
2
22
43
42
41
40
25
26
27
28
32
14
31
15
30
16
29
17
11
12
TC7129CLW
F1, E1, DP1
B2, C2, BATT
A2, G2, D2
F2, E2, DP2
B3, C3, MINUS
A3, G3, D3
F3, E3, DP3
B4, C4, BC5
A4, G4, D4
F4, E4, DP4
NC
REF LO
REF HI
IN HI
IN LO
BUFF
C
REF
C
+
REF
COM
CONT
INT OUT
NC
A
1
, G
1
, D
1
B
1
, C
1
, CONT
A.D.
OSC
3
OSC
1
NC
OSC
2
DP
1
DP
2
RANGE
DGND
BP
3
BP
2
BP
1
V
DISP
DP
4
/OR
NC
DP
3
/UR
LATCH/HOLD
V
+
V
INT IN
27
28
29
30
31
32
33
7
4
3
2
1
TC7129CKW
12
13
14
15
17
18
44
43
42
41
39
38
40
16
37
36
35
34
19
20
21
22
26
8
25
9
24
10
23
11
5
6
A
1
, G
1
, D
1
B
1
, C
1
, CONT
A.D.
OSC
3
OSC
1
NC
OSC
2
DP
1
DP
2
RANGE
DGND
REF LO
REF HI
IN HI
IN LO
BUFF
C
REF
C
+
REF
COM
CONT
INT OUT
NC
F1, E1, DP1
B2, C2, BATT
A2, G2, D2
F2, E2, DP2
B3, C3, MINUS
A3, G3, D3
F3, E3, DP3
B4, C4, BC5
A4, G4, D4
F4, E4, DP4
NC
BP
3
BP
2
BP
1
V
DISP
DP
4
/OR
NC
DP
3
/UR
LATCH/HOLD
V
+
V
INT IN
TC7129CPL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
OSC2
DP1
DP2
RANGE
DGND
REF LO
REF HI
IN HI
IN LO
BUFF
C
REF
C
+
REF
COM
CONT
INT OUT
INT IN
V
+
V
DP3/UR
OSC1
OSC3
ANNUNICATOR DRIVE
B1, C1, CONT
A1, G1, D1
F1, E1, DP1
B2, C2, LO BATT
A2, G2, D2
F2, E2, DP2
B3, C3, MINUS
A3, G3, D3
F3, E3, DP3
B4, C4, BC5
A4, G4, D4
F4, E4, DP4
BP3
BP2
BP1
VDISP
DP4/OR
DISPLAY
OUTPUT
LINES
LATCH/HOLD
PIN CONFIGURATIONS
44-Pin PLCC
44-Pin QFP
40-Pin PDIP
"Weak Output" Current
Pins 20, 21 Sink/Source
--
3/3
--
A
Sink/Source
Pin 27 Sink/Source
--
3/9
--
A
Pin 22 Source Current
--
40
--
A
Pin 22 Sink Current
--
3
--
A
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
ELECTRICAL CHARACTERISTICS:
V
+
to V
= 9V, V
REF
= 1V, T
A
= +25
C, f
CLK
= 120 kHz, unless otherwise
indicated. Pin numbers refer to 40-pin DIP.
TC7129
4-1/2 DIGIT ANALOG-TO-DIGITAL
CONVERTER WITH ON-CHIP LCD DRIVERS
3-234
TELCOM SEMICONDUCTOR, INC.
TC7129
4-1/2 DIGIT ANALOG-TO-DIGITAL
CONVERTER WITH ON-CHIP LCD DRIVERS
PIN DESCRIPTIONS
Pin No.
Pin No.
Pin No.
40-Pin
44-Pin
44-Pin
TC7129CPL
TC7129CKW
TC7129CLW
Symbol
Function
1
40
2
OSC
1
Input to first clock inverter.
2
41
3
OSC
3
Output of second clock inverter.
3
ANNUNCIATOR
Backplane square-wave output for driving annunciators.
4
43
5
B
1
, C
1
, CONT
Output to display segments.
5
44
6
A
1
, G
1
, D
1
Output to display segments.
6
1
7
F
1
, E
1
, DP
1
Output to display segments.
7
2
8
B
2
, C
2
, LO BATT
Output to display segments.
8
3
9
A
2
, G
2
, D
2
Output to display segments.
9
4
10
F
2
, E
2
, DP
2
Output to display segments.
10
5
11
B
3
, C
3
, MINUS
Output to display segments.
11
7
13
A
3
, G
3
, D
3
Output to display segments.
12
8
14
F
3
, E
3
, DP
3
Output to display segments.
13
9
15
B
4
, C
4
, BC
5
Output to display segments.
14
10
16
A
4
, D
4
, G
4
Output to display segments.
15
11
17
F
4
, E
4
, DP
4
Output to display segments.
16
12
18
BP
3
Backplane #3 output to display.
17
13
19
BP
2
Backplane #2 output to display.
18
14
20
BP
1
Backplane #1 output to display.
19
15
21
V
DISP
Negative rail for display drivers.
20
16
22
DP
4
/OR
Input: When HI, turns on most significant decimal point.
Output: Pulled HI when result count exceeds
19,999.
21
18
24
DP
3
/UR
Input: Second most significant decimal point on when HI.
Output: Pulled HI when result count is less than
1000.
22
19
25
LATCH/HOLD
Input: When floating, ADC operates in the free-run mode.
When pulled HI, the last displayed reading is held. When
pulled LO, the result counter contents aren shown
inincrementing during the deintegrate phase of cycle.
Output: Negative-going edge occurs when the data latches
are updated. Can be used for converter status signal.
23
20
26
V
Negative power supply terminal.
24
27
V
+
Positive power supply terminal and positive rail for display
drivers.
25
21
28
INT IN
Input to integrator amplifier.
26
23
29
INT OUT
Output of integrator amplifier.
27
24
30
CONTINUITY
Input: When LO, continuity flag on the display is OFF.
When HI, continuity flag is ON.
Output: HI when voltage between inputs is less than +200
mV. LO when voltage between inputs is more than +200
mV.
28
25
31
COMMON
Sets common-mode voltage of 3.2V below V
+
for DE,
10X, etc. Can be used as preregulator for external
reference.
29
26
32
C
+
REF
Positive side of external reference capacitor.
30
27
33
C
REF
Negative side of external reference capacitor.
31
29
35
BUFFER
Output of buffer amplifier.
32
30
36
IN LO
Negative input voltage terminal.
33
31
37
IN HI
Positive input voltage terminal.
3-235
TELCOM SEMICONDUCTOR, INC.
7
6
5
4
3
1
2
8
PIN DESCRIPTIONS
Pin No.
Pin No.
Pin No.
40-Pin
44-Pin
44-Pin
TC7129CPL
TC7129CKW
TC7129CLW
Symbol
Function
34
32
38
REF HI
Positive reference voltage in
35
33
39
REF LO
Negative reference voltage
36
34
40
DGND
Internal ground reference for digital section. See "
5V Power
Supply" paragraph.
37
35
41
RANGE
3
A pull-down for 200 mV scale. Pulled HI externally for 2V
scale.
38
36
42
DP
2
Internal 3
A pull-down. When HI, decimal point 2 will be on.
39
37
43
DP
1
Internal 3
A pull-down. When HI, decimal point 1 will be on.
40
38
44
OSC
2
Output of first clock inverter. Input of second clock inverter.
6,17, 28, 39
12, 23, 34,1
NC
No Connection
COMPONENT SELECTION
(All pin designations refer to 40-Pin Dip)
The TC7129 is designed to be the heart of a high-
resolution analog measurement instrument. The only addi-
tional components required are a few passive elements, a
voltage reference, an LCD, and a power source. Most
component values are not critical; substitutes can be chosen
based on the information given below.
The basic circuit for a digital multimeter application is
shown in Figure 1. See "Special Applications" for variations.
Typical values for each component are shown. The sections
below give component selection criteria.
Oscillator (X
OSC
, C
O1
, C
O2
, R
O
)
The primary criterion for selecting the crystal oscillator
is to chose a frequency that achieves maximum rejection of
line-frequency noise. To do this, the integration phase
should last an integral number of line cycles. The integration
phase of the TC7129 is 10,000 clock cycles on the 200 mV
range and 1000 clock cycles on the 2V range. One clock
cycle is equal to two oscillator cycles. For 60 Hz rejection, the
oscillator frequency should be chosen so that the period of
one line cycle equals the integration time for the 2V range:
1/60 second = 16.7 msec =
1000 clock cycles 2 osc cycles/clock cycle
oscillator frequency
giving an oscillator frequency of 120 kHz. A similar calcula-
tion gives an optimum frequency of 100 kHz for 50 Hz
rejection.
*
,
The resistor and capacitor values are not critical; those
shown work for most applications. In some situations, the
capacitor values may have to be adjusted to compensate for
parasitic capacitance in the circuit. The capacitors can be
low-cost ceramic devices.
Some applications can use a simple RC network instead
of a crystal oscillator. The RC oscillator has more potential
for jitter, especially in the least significant digit. See "RC
Oscillator."
Integrating Resistor (R
INT
)
The integrating resistor sets the charging current for
the integrating capacitor. Choose a value that provides a
current between 5
A and 20
A at 2V, the maximum full-
scale input. The typical value chosen gives a charging
current of 13.3
A:
I
CHARGE
= 13.3
A
Too high a value for R
INT
increases the sensitivity to
noise pickup and increases errors due to leakage current.
Too low a value degrades the linearity of the integration,
leading to inaccurate readings.
2V
150 k
TC7129
4-1/2 DIGIT ANALOG-TO-DIGITAL
CONVERTER WITH ON-CHIP LCD DRIVERS
3-236
TELCOM SEMICONDUCTOR, INC.
TC7129
4-1/2 DIGIT ANALOG-TO-DIGITAL
CONVERTER WITH ON-CHIP LCD DRIVERS
Figure 1. Standard Circuit
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
9V
+
TC04
LOW BATTERY CONTINUITY
V
+
5 pF
120
kHz
10 pF
0.1 F
20
k
0.1
F
100 k
CINT
0.1
F
V
+
V
IN
+
+
330 k
CRYSTAL
RO
CO2
CRF
DREF
RREF
CIF
RIF
CREF
1 f
10 k
RBIAS
150 k
RINT
OSC
1
OSC
3
ANNUNC
V
DISP
DP
4
/OR
DISPLAY DRIVE OUTPUTS
DP
3
/UR
LATCH/
HOLD
V
V
+
INT IN
INT OUT
CONTINUITY
COMMON
C
REF
+
C
REF
BUFFER
IN LO
IN HI
REF HI
REF LO
DGND
RANGE
DP
2
DP
1
OSC
2
TC7129
CO1
3-237
TELCOM SEMICONDUCTOR, INC.
7
6
5
4
3
1
2
8
TC7129
4-1/2 DIGIT ANALOG-TO-DIGITAL
CONVERTER WITH ON-CHIP LCD DRIVERS
Integrating Capacitor (C
INT
)
The charge stored in the integrating capacitor during
the integrate phase is directly proportional to the input
voltage. The primary selection criterion for C
INT
is to choose
a value that gives the highest voltage swing while remain-
ing within the high-linearity portion of the integrator output
range. An integrator swing of 2V is the recommended
value. The capacitor value can be calculated from the
equation:
C
INT
=
,
where t
INT
is the integration time.
Using the values derived above (assuming 60 Hz
operation), the equation becomes:
C
INT
= = 0.1
F.
The capacitor should have low dielectric absorption to
ensure good integration linearity. Polypropylene and Teflon
capacitors are usually suitable. A good measurement of the
dielectric absorption is to connect the reference capacitor
across the inputs by connecting:
Pin to Pin
20
33
(C
REF
+
to IN HI)
30
32
(C
REF
to IN LO)
A reading between 10,000 and 9998 is acceptable;
anything lower indicates unacceptably high dielectric ab-
sorption.
Reference Capacitor (C
REF
)
The reference capacitor stores the reference voltage
during several phases of the measurement cycle. Low
leakage is the primary selection criterion for this component.
The value must be high enough to offset the effect of stray
capacitance at the capacitor terminals. A value of at least
1
F is recommended.
Voltage Reference (D
REF
, R
REF
, R
BIAS
, C
RF
)
A TC04 band-gap reference provides a high-stability
voltage reference of 1.25V. The reference potentiometer
(R
REF
) provides an adjustment for adjusting the reference
voltage; any value above 20 k
is adequate. The bias
resistor (R
BIAS
) limits the current through D
REF
to less than
150
A. The reference filter capacitor (C
RF
) forms an RC
filter with R
BIAS
to help eliminate noise.
Input filter (R
IF
, C
IF
)
For added stability, an RC input noise filter is usually
included in the circuit. The input filter resistor value should
not exceed 100 k
. A typical RC time constant value is
16.7msec to help reject line-frequency noise. The input filter
capacitor should have low leakage for a high-impedance
input.
Battery
The typical circuit uses a 9V battery as a power source.
Any value between 6V and 12V can be used. For operation
from batteries with voltages lower than 6V and for operation
from power supplies, see "Powering the TC7129."
SPECIAL APPLICATIONS
The TC7129 as a Replacement Part
The TC7129 is a direct pin-for-pin replacement part for
the ICL7129. Note, however, that part requires a capacitor
and resistor between pins 26 and 28 for phase compensa-
tion. Since the TC7129 uses internal phase compensation,
these parts are not required and, in fact, must be removed
from the circuit for stable operation.
Powering the TC7129
While the most common power source for the TC7129
is a 9V battery, there are other possibilities. Some of the
more common ones are explained below.
16.7msec x 13.3
A
2V
t
INT
x I
INT
V
SWING
3-238
TELCOM SEMICONDUCTOR, INC.
TC7129
4-1/2 DIGIT ANALOG-TO-DIGITAL
CONVERTER WITH ON-CHIP LCD DRIVERS
Figure 2. Powering the TC7129 From a
5V Power Supply
V
V
+
REF HI
REF LO
IN HI
COM
IN LO
DGND
VIN
+
5V
0.1 F
+5V
0.1 F
24
34
35
28
33
32
23
36
TC7129
TC04
0.1 F
5V Power Supply
Measurements are made with respect to power supply
ground. DGND (pin 36) is set internally to about 5V less than
V
+
(pin 24); it is not intended as a power supply input and
must not be tied directly to power supply ground. (It can be
used as a reference for external logic, as explained in
"Connecting to External Logic." (See Figure 2.)
V
TC7129
V
REF HI
REF LO
IN HI
COM
IN LO
DGND
3.8V
TO
6V
+
+
10 F
+
8
2
4
10 F
TC04
+
3
TC7660
VIN
5
24
+
34
35
28
33
32
23
36
Figure 3. Powering the TC7129 From a Low-Voltage Battery
V
V
DGND
+
10 F
+
8
2
4
10 F
TC04
+
3
VIN
5
24
+
34
35
28
33
32
23
36
TC7660
V
+
GND
0.1 F
0.1 F
+5V
TC7129
Figure 4. Powering the TC7129 From a +5V Power Supply
Low-Voltage Battery Source
A battery with voltage between 3.8V and 6V can be used
to power the TC7129 when used with a voltage-doubler
circuit as shown in Figure 3. The voltage doubler uses the
TC7660 DC-to-DC voltage converter and two external ca-
pacitors.
+5V Power Supply
Measurements are made with respect to power supply
ground. COMMON (pin 28) is connected to REF LO (pin 35).
A voltage doubler is needed, since the supply voltage is less
than the 6V minimum needed by the TC7129. DGND (pin
36) must be isolated from power supply ground.
(See Figure 4.)
Connecting to External Logic
External logic can be directly referenced to DGND (pin
36), provided that the supply current of the external logic
does not exceed the sink current of DGND (Figure 5). A safe
value for DGND sink current is 1.2 mA. If the sink current is
expected to exceed this value, a buffer is recommended.
(See Figure 6.)
3-239
TELCOM SEMICONDUCTOR, INC.
7
6
5
4
3
1
2
8
Figure 5. External Logic Referenced Directly to DGND
Figure 6. External Logic Referenced to DGND With Buffer
Temperature Compensation
For most applications, V
DISP
(pin 19) can be connected
directly to DGND (pin 36). For applications with a wide
temperature range, some LCDs require that the drive levels
vary with temperature to maintain good viewing angle and
display contrast. Figure 7 shows two circuits that can be
adjusted to give temperature compensation of about 10
mV/
C between V
+
(pin 24) and V
DISP
. The diode between
DGND and V
DISP
should have a low turn-ON voltage be-
cause V
DISP
cannot exceed 0.3V below DGND.
EXTERNAL
LOGIC
DGND
V
+
36
24
23
ILOGIC
TC7129
V
+
EXTERNAL
LOGIC
ILOGIC
DGND
23
24
V
+
36
TC7129
V
TC7129
+
1N4148
5 k
75 k
200 k
39 k
19
36
24
23
V
V+
VDISP
DGND
TC7129
2N2222
39 k
19
36
24
23
V
V+
VDISP
DGND
20 k
18 k
Figure 7. Temperature Compensating Circuits
TC7129
4-1/2 DIGIT ANALOG-TO-DIGITAL
CONVERTER WITH ON-CHIP LCD DRIVERS
3-240
TELCOM SEMICONDUCTOR, INC.
TC7129
4-1/2 DIGIT ANALOG-TO-DIGITAL
CONVERTER WITH ON-CHIP LCD DRIVERS
RC Oscillator
For applications in which 3-1/2 digit (100
V) resolution
is sufficient, an RC oscillator is adequate. A recommended
value for the capacitor is 51 pF. Other values can be used as
long as they are sufficiently larger than the circuit parasitic
capacitance. The resistor value is calculated from:
R =
For 120 kHz frequency and C = 51 pF, the calculated
value of R is 75 k
. The RC oscillator and the crystal
oscillator circuits are shown in Figure 8.
Measuring Techniques
Two important techniques are used in the TC7129:
successive integration and digital auto-zeroing. Successive
integration is a refinement to the traditional dual-slope
conversion technique.
Dual-Slope Conversion
A dual-slope conversion has two basic phases: inte-
grate and deintegrate. During the integrate phase, the input
signal is integrated for a fixed period of time; the integrated
voltage level is thus proportional to the input voltage. During
the deintegrate phase, the integrated voltage is ramped
down at a fixed slope, and a counter counts the clock cycles
until the integrator voltage crosses zero. The count is a
Figure 8. Oscillator Circuits
0.45
freq C
*
measurement of the time to ramp the integrated voltage to
zero, and is therefore proportional to the input voltage being
measured. This count can then be scaled and displayed as
a measurement of the input voltage. Figure 9 shows the
phases of the dual-slope conversion.
The dual-slope method has a fundamental limitation.
The count can only stop on a clock cycle, so that measure-
ment accuracy is limited to the clock frequency. In addition,
a delay in the zero-crossing comparator can add to the
inaccuracy. Figure 10 shows these errors in an actual
measurement.
Successive Integration
The successive integration technique picks up where
dual-slope conversion ends. The overshoot voltage shown
in Figure 10, called the "integrator residue voltage," is
measured to obtain a correction to the initial count. Figure 11
shows the cycles in a successive integration measurement.
The waveform shown is for a negative input signal. The
sequence of events during the measurement cycle is:
Phase
Description
INT
1
Input signal is integrated for fixed time. (1000 clock
cycles on 2V scale, 10,000 on 200 mV)
DE
1
Integrator voltage is ramped to zero. Counter counts
up until zero crossing to produce reading accurate
to 3-1/2 digits. Residue represents an overshoot of
the actual input voltage.
REST
Rest; circuit settles.
X10
Residue voltage is amplified 10 times and inverted.
DE
2
Integrator voltage is ramped to zero. Counter counts
down until zero crossing to correct reading to 4-1/2
digits. Residue represents an undershoot of the
actual input voltage.
REST
Rest; circuit settles.
X10
Residue voltage is amplified 10 times and inverted.
DE
3
Integrator voltage is ramped to zero. Counter counts
up until zero crossing to correct reading to 5-1/2
digits. Residue is discarded.
Figure 9. Dual-Slope Conversion
DEINTEGRATE
ZERO
CROSSING
TIME
INTEGRATE
TC7129
TC7129
1
40
2
270 k
10 pF
V
+
120 kHz
5 pF
V
+
1
40
2
51 pF
75 k
3-241
TELCOM SEMICONDUCTOR, INC.
7
6
5
4
3
1
2
8
INTEGRATE
DEINTEGRATE
TIME
CLOCK PULSES
OVERSHOOT DUE TO ZERO CROSSING
BETWEEN CLOCK PULSES
INTEGRATOR RESIDUE VOLTAGE
OVERSHOOT CAUSED BY
COMPARATOR DELAY OF
1 CLOCK PULSE
Figure 10. Accuracy Errors in Dual-Slope Conversion
Figure 11. Integrator Waveform
INT1
INTEGRATE
DE1
DEINTEGRATE
REST X10
ZERO
INTEGRATE
AND LATCH
DE2 REST X10
DE3
ZERO INTEGRATE
INTEGRATOR
RESIDUAL VOLTAGE
TC7129
NOTE:
Shaded area greatly expanded
in time and amplitude.
Inside the TC7129
Figure 12 shows a simplified block diagram of the
TC7129.
Integrator Section
The integrator section includes the integrator, compara-
tor, input buffer amplifier, and analog switches used to
change the circuit configuration during the separate mea-
surement phases described earlier.
Digital Auto-Zeroing
To eliminate the effect of amplifier offset errors, the
TC7129 uses a digital auto-zeroing technique. After the
input voltage is measured as described above, the mea-
surement is repeated with the inputs shorted internally. The
reading with inputs shorted is a measurement of the internal
errors and is subtracted from the previous reading to obtain
a corrected measurement. Digital auto-zeroing eliminates
the need for an external auto-zeroing capacitor used in other
ADCs.
TC7129
4-1/2 DIGIT ANALOG-TO-DIGITAL
CONVERTER WITH ON-CHIP LCD DRIVERS
3-242
TELCOM SEMICONDUCTOR, INC.
TC7129
4-1/2 DIGIT ANALOG-TO-DIGITAL
CONVERTER WITH ON-CHIP LCD DRIVERS
LOW BATTERY CONTINUITY
SEGMENT DRIVES
BACKPLANE
DRIVES
LATCH, DECODE DISPLAY MULTIPLEXER
UP/DOWN RESULTS COUNTER
SEQUENCE COUNTER/DECODER
CONTROL LOGIC
ANALOG SECTION
OSC1
OSC2
OSC3
RANGE
L/H
CONT
V+
V
DGND
COMMON
IN
HI
IN
LO
BUFF
DP1
DP2
UR/DP3
OR/DP4
REF HI
REF LO
INT OUT
INT IN
ANNUNCIATOR
DRIVE
VDISP
TC7129
Figure 12. Functional Block Diagram
3-243
TELCOM SEMICONDUCTOR, INC.
7
6
5
4
3
1
2
8
TC7129
4-1/2 DIGIT ANALOG-TO-DIGITAL
CONVERTER WITH ON-CHIP LCD DRIVERS
Figure 13. Integrator Block Diagram
The buffer amplifier has a common-mode input voltage
range from 1.5V above V
to 1V below V
+
. The integrator
amplifier can swing to within 0.3V of the rails, although for
best linearity the swing is usually limited to within 1V. Both
amplifiers can supply up to 80
A of output current, but
should be limited to 20
A for good linearity.
Continuity Indicator
A comparator with a 200 mV threshold is connected
between IN HI (pin 33) and IN LO (pin 32). Whenever the
voltage between inputs is less than 200 mV, the
CONTINUITY output (pin 27) will be pulled HIGH, activating
the continuity annunciator on the display. The continuity
pin can also be used as an input to drive the continuity
annunciator directly from an external source. A schematic
of the input/output nature of this pin is shown in Figure 15.
Figure 14. Continuity Indicator Circuit
COM
BUFFER
200 mV
IN HI
+
IN LO
+
V
CONT
500 k
TO DISPLAY
DRIVER
(NOT LATCHED)
TC7129
COMMON
REF HI
BUFFER
INTE-
GRATOR
DE
ZI, X10
COMPARATOR 1
200 mV
CREF
RINT
CINT
INT1
IN HI
+
+
+
REF LO
DE
IN LO
+
DE
DE+
DE+
DE
100 pF
V
+
CONTINUITY
INT1, INT2
CONTINUITY
COMPARATOR
500 k
REST
TO DISPLAY DRIVER
10
pF
COMPARATOR 2
TO DIGITAL
SECTION
TC7129
INT
X10
Table I. Switch Legends
Label
Meaning
DE
Open during all deintegrate phases.
DE
Closed during all deintegrate phases when input
voltage is negative.
DE+
Closed during all deintegrate phases when input
voltage is positive.
INT
1
Closed during the first integrate phase
(measurement of the input voltage).
INT
2
Closed during the second integrate phase
(measurement of the amplifier offset).
INT
Open during both integrate phases.
REST
Closed during the rest phase.
ZI
Closed during the zero-integrate phase.
X10
Closed during the X10 phase.
X10
Open during the X10 phase.
3-244
TELCOM SEMICONDUCTOR, INC.
Sequence and Results Counter
A sequence counter and associated control logic pro-
vide signals that operate the analog switches in the integra-
tor section. The comparator output from the integrator gates
the results counter. The results counter is a six-section up/
down decade counter which holds the intermediate results
from each successive integration.
Overrange and Underrange Outputs
When the results counter holds a value greater than
19,999, the DP
4
/OR output (pin 20) is driven HIGH. When
the results counter value is less than
1000, the DP
3
/UR
output (pin 21) is driven HIGH. Both signals are valid on the
falling edge of LATCH/HOLD (L/H) and do not change until
the end of the next conversion cycle. The signals are
updated at the end of each conversion unless the L/H input
(pin 22) is held HIGH. Pins 20 and 21 can also be used as
inputs for external control of decimal points 3 and 4. Figure
15 shows a schematic of the input/output nature of these
pins.
Latch/Hold
The L/H output goes LOW during the last 100 cycles of
each conversion. This pulse latches the conversion data into
the display driver section of the TC7129. This pin can also
be used as an input. When driven HIGH, the display will not
be updated; the previous reading is displayed. When driven
LOW, the display reading is not latched; the sequence
counter reading will be displayed. Since the counter is
counting much faster than the backplanes are being up-
dated, the reading shown in this mode is somewhat erratic.
Display Driver
The TC7129 drives a triplexed LCD with three back-
planes. The LCD can include decimal points, polarity sign,
and annunciators for continuity and low battery. Figure 17
shows the assignment of the display segments to the
backplanes and segment drive lines. The backplane drive
frequency is obtained by dividing the oscillator frequency by
1200. This results in a backplane drive frequency of 100 Hz
for 60 Hz operation (120 kHz crystal) and 83.3 Hz for 50 Hz
operation (100 kHz crystal).
Backplane waveforms are shown in Figure 18. These
appear on outputs BP
1
, BP
2
, BP
3
(pins 16, 17, and 18). They
remain the same regardless of the segments being driven.
Other display output lines (pins 4 through 15) have
waveforms that vary depending on the displayed values.
Figure 19 shows a set of waveforms for the A, G, D outputs
(pins 5, 8, 11, and 14) for several combinations of "ON"
segments.
TC7129
4-1/2 DIGIT ANALOG-TO-DIGITAL
CONVERTER WITH ON-CHIP LCD DRIVERS
+
12 A
P
TC7129
LOGIC
SECTION
5V
3.2V
N
N
V
+
V
COM
DGND
24
28
36
23
TC7129
500 k
DP4/OR, PIN 20
DP3/UR, PIN 21
LATCH/HOLD PIN 22
CONTINUITY, PIN 27
Figure 15. Input/Output Pin Schematic
Common and Digital Ground
The common and digital ground (DGND) outputs are
generated from internal zener diodes. The voltage between
V
+
and DGND is the internal supply voltage for the digital
section of the TC7129. Common can source approximately
12
A; DGND has essentially no source capability.
Low Battery
The low battery annunciator turns on when supply
voltage between V
+
and V
drops below 6.8V. The internal
zener has a threshold of 6.3V. When the supply voltage
drops below 6.8V, the transistor tied to V
turns OFF, pulling
the "Low Battery" point HIGH. (See Figure 16.)
Figure 16. Digital Ground (DGND) and Common Outputs
3-245
TELCOM SEMICONDUCTOR, INC.
7
6
5
4
3
1
2
8
Figure 17. Display Segment Assignments
The ANNUNCIATOR DRIVE output (pin 3) is a square-
wave running at the backplane frequency (100 Hz or 83.3 Hz),
with a peak-to-peak voltage equal to DGND voltage. Con-
necting an annunciator to pin 3 turns it ON; connecting it to
its backplane turns it OFF.
Figure 18. Backplane Waveforms
BP1
BP2
BP3
LOW BATTERY
LOW BATTERY
CONTINUITY
F4, E4, DP4
A4, G4, D4
B4, C4, BC4
F3, E3, DP3
A3, G3, D3
B3, C3, MINUS
B1, C1, CONTINUITY
A1, G1, D1
F1, E1, DP1
B2, C2, LOW BATTERY
A2, G2, D2
BACKPLANE
CONNECTIONS
F2, E2, DP2
CONTINUITY
BP1
BP2
BP3
Figure 19. Typical Display Output Waveforms
VDD
VH
VL
VDISP
VDD
VH
VL
VDISP
VDD
VH
VL
VDISP
VDD
VH
VL
VDISP
b SEGMENT
LINE
ALL OFF
a SEGMENT
ON
d, g OFF
a, g ON
d OFF
ALL ON
TC7129
4-1/2 DIGIT ANALOG-TO-DIGITAL
CONVERTER WITH ON-CHIP LCD DRIVERS
PDF 
ZIP