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Электронный компонент: TC71EPA

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5-7
TELCOM SEMICONDUCTOR, INC.
7
6
5
4
3
1
2
8
TC70/71
MICROMASTERTM SYSTEM SUPERVISOR WITH POWER SUPPLY
MONITOR, WATCHDOG AND BATTERY BACKUP
VCC
VCCO
VBATT
TC70/71
CEI
(TC70)
V
DETECTOR
WATCHDOG
TIMER
WDD
(TC70)
CEO
(TC70)
TDO
(TC71)
VREF1
VREF2
VREF3
PF
(TC71)
TDI
(TC71)
RS
BATTERY
BACK-UP
CONTROL
DELAY
TIMER
GND
PIN CONFIGURATIONS (DIP and SOIC)
1
8
2
7
3
6
4
5
TC70
1
8
2
7
3
6
4
5
TC71
CEO
VCCO
GND
CEI
VCC
VCCO
GND
TDI
VCC
WDD
VBATT
RS
TDO
PF
VBATT
RS
ORDERING INFORMATION
Part No.
Package
Temp. Range
TC70COA
8-Pin SOIC
0
C to +70
C
TC70CPA
8-Pin Plastic DIP
0
C to +70
C
TC70EOA
8-Pin SOIC
40
C to +85
C
TC70EPA
8-Pin Plastic DIP
40
C to +85
C
TC71COA
8-Pin SOIC
0
C to +70
C
TC71CPA
8-Pin Plastic DIP
0
C to +70
C
TC71EOA
8-Pin SOIC
40
C to +85
C
TC71EPA
8-Pin Plastic DIP
40
C to +85
C
FUNCTIONAL BLOCK DIAGRAM
FEATURES
s
Maximum Functional Integration: Precision Power
Supply Monitor, Watchdog Timer, External RESET
Override, Threshold Detector and Battery Backup
Controller in an 8-Pin Package
s
Generates Power-on RESET and Guards Against
Unstable Processor Operation Resulting from
Power "Brown-out"
s
Automatically Halts and Restarts an Out-of-
Control Microprocessor
s
Output Can be Wire-ORed, or Hooked to Manual
RESET Pushbutton Switch
s
Watchdog Disable Pin for Easier Prototyping
(TC70)
s
Voltage Monitor for Power Fail or Low Battery
Warning (TC71)
s
Available in 8-Pin Plastic DIP or 8-Pin SOIC
Packages
s
Cost Effective
TYPICAL APPLICATIONS
s
All Microprocessor-based Systems
s
Test Equipment
s
Instrumentation
s
Set-Top Boxes
GENERAL DESCRIPTION
The TC70/71 is a fully-integrated power supply monitor,
watchdog and battery backup circuit in a space-saving
8-pin package.
When power is initially applied, the TC70/71 holds the
processor in its reset state for a minimum of 500msec after
V
CC
is in tolerance to ensure stable system start-up. After
start-up, processor sanity is monitored by the on-board
watchdog circuit. The processor must provide periodic high-
to-low level transitions to the TC70/71 to verify proper
execution. Should the processor fail to supply this signal
within the specified timeout period, an out-of-control proces-
sor is indicated and the TC70/71 issues a momentary
processor reset as a result. The TC70 also features a
watchdog disable pin to facilitate system test and debug.
The output of the TC70/71 can be wire-ORed to a push-
button switch (or electronic signal) to reset the processor.
When connected to a push-button switch, the TC70/71
provides contact debounce.
The integrated battery backup circuit on-board the TC70/
71 converts CMOS RAM into nonvolatile memory by first
write-protecting, then switching the V
CC
line of the RAM over
to an external battery.
The TC71 incorporates an additional 1.3V threshold
detector for power fail warning, low battery detection or to
monitor power supply voltages other than +5V.
TC70/71-1 11/18/96
5-8
TELCOM SEMICONDUCTOR, INC.
MICROMASTERTM SYSTEM SUPERVISOR
WITH POWER SUPPLY MONITOR, WATCHDOG
AND BATTERY BACKUP
*This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of
the specifications is not implied. Exposure to Absolute Maximum Rating
Conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS*
Voltage (Any Pin) with Respect to
Ground ................................ GND 0.3 to V
CC
+ 0.3V
Operating Temperature Range ............... 40
C to +85
C
Storage Temperature Range ................ 65
C to +150
C
Lead Temperature (Soldering, 10 sec) ................. +300
C
TC70/71
ELECTRICAL CHARACTERISTICS:
Recommended DC Operations
: T
A
= T
MIN
to T
MAX,
unless otherwise specified.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
V
CC
Supply Voltage
Note 1
4.5
5.0
5.5
V
V
IH
Input HIGH Level
CEI, WDD (Note 1)
2.5
--
--
V
V
IH
Input HIGH Level
RS (Note 1)
2.2
--
--
V
V
IL
Input LOW Level
CEI, WDD, RS (Note 1)
--
--
0.8
V
ELECTRICAL CHARACTERISTICS:
DC
: T
A
= T
MIN
to T
MAX
, V
CC
= 4.5V to 5.5V, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
I
CC1
Operating Current
Notes 2, 3
--
5
6.5
mA
I
CC2
Operating Current in
V
CC
= 0; V
BATT
= 2.8V; (Note 3)
--
0.01
0.20
A
Battery Backup Mode
I
IH
Input Leakage
CEI
--
4
7
A
I
IL
Input Leakage
CEI
--
1
--
A
I
IH
Input Leakage
RS
--
1
--
A
I
STBY
Battery Standby Current
5.5V > V
CC
> V
BATT
+ 0.2V
1.0
--
0.02
A
I
STBY
Battery Standby Current
5.5V > V
CC
> V
BATT
+ 0.2V
0.1
--
0.02
A
T
A
= 25
C
ELECTRICAL CHARACTERISTICS:
DC
: Power Supply Monitor, EXT. RESET and Watchdog: T
A
= T
MIN
to T
MAX
, V
CC
= 4.5V to 5.5V, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
I
OL
Output Current 0.4V
V
OL
= 0.4V
2
5
--
mA
(RS, TDO, CEO, PF Pins)
I
OH
Output Current 2.4V
V
OH
= 2.4V
2
3
--
mA
(TDO, CEO, PF Pins)
WDD
I
WDD Input Current
WDD = GND
120
--
--
A
WDD = V
CC
--
--
25
V
STH
RS Strobe (HIGH) Level
Figure 3 (Note 1)
V
DD
0.5
--
--
V
V
STL
RS Strobe (LOW) Level
Figure 3 (Note 1)
2.2
--
V
DD
1.8
V
V
CCTRIP
V
CC
Trip Point
(Note 1) 0
C
T
A
70
C
4.25
--
4.49
40
C
T
A
85
C
4.20
4.49
ELECTRICAL CHARACTERISTICS:
DC
: Battery Backup and Threshold Detector: T
A
= T
MIN
to T
MAX
, V
CC
= 4.5V to 5.5V, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
V
OUT1
V
CCO
Output Voltage
I
OUT
= 1mA
V
CC
0.3 V
CC
0.1
--
V
I
OUT
= 50mA
V
CC
0.5 V
CC
0.20
--
V
OUT2
V
OUT
in Battery Backup Mode
I
OUT
= 250
A, V
CC
< V
BATT
0.2, V
BATT
= 2.8V V
BATT
0.1 V
BATT
0.02 --
V
5-9
TELCOM SEMICONDUCTOR, INC.
7
6
5
4
3
1
2
8
ELECTRICAL CHARACTERISTICS: (Cont.)
DC
: Battery Backup and Threshold Detector: T
A
= T
MIN
to T
MAX
, V
CC
= 4.5V to 5.5V, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
I
OUT1
V
CCO
Output Current
V
CC
= 4.5V, V
CCO
= 3.5V
50
100
--
mA
I
OUT2
V
CCO
Output Current in
V
CCO
= V
BATT
0.3V
500
--
--
A
Battery Backup Mode
V
BATT
= 2.8V
V
SW
Battery Switchover Threshold
--
V
BATT
0.01
--
V
(V
CC
Falling)
V
HYST
Battery Switchover Hysteresis
--
20
--
mV
VOH
CEO
CEO Output Voltage in
V
CC
< V
BATT
0.2, V
BATT
= 2.8V
V
BATT
0.2
--
--
V
Battery Backup Mode
I
OH
= 10
A
V
TDI
Threshold Detector Trip Voltage
1.2
--
1.4
V
I
TDI
Threshold Detector Input Current
T
A
= 25
C
25
--
+25
nA
V
TDI (HYST)
Threshold Detector Hysteresis
--
10
--
mV
ELECTRICAL CHARACTERISTICS:
AC
: Power Supply Monitor, EXT. RESET and Watchdog: T
A
= T
MIN
to T
MAX
, V
CC
= 4.5V to 5.5V, unless otherwise
specified.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
t
PBH
PB Hold Time
Figure 4 (Note 4)
20
--
--
msec
t
RST
Reset Active Time
Figure 6
500
--
900
msec
t
ST
RS STROBE Pulsewidth
Figure 3
500
--
--
nsec
t
TD
Watchdog Timeout Period
Figure 3
500
700
900
msec
t
RPD
V
CC
Detect to RS LOW
Figure 6
--
--
100
nsec
ELECTRICAL CHARACTERISTICS:
AC
: Battery Backup and Threshold Detector: T
A
= T
MIN
to T
MAX
, V
CC
= 4.5V to 5.5V, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
t
PD
CE Propagational Delay
Figure 7
--
--
50
nsec
ELECTRICAL CHARACTERISTICS:
AC
: T
A
= T
MIN
to T
MAX
.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
t
F
V
CC
Fall Time From
Figure 5 (Note 1)
10
--
--
sec
4.25V to 3.0V
t
R
V
CC
Rise Time From
Figure 5 (Note 1)
0
--
--
sec
3.0V to 4.25V
NOTES: 1. All voltages referenced to ground.
2. No output load.
3
Measured with V
CCO
and CEO open.
4. The RS output must be held low for a minimum of 20msec to guarantee a reset.
TC70/71
MICROMASTERTM SYSTEM SUPERVISOR
WITH POWER SUPPLY MONITOR, WATCHDOG
AND BATTERY BACKUP
5-10
TELCOM SEMICONDUCTOR, INC.
strobed within the watchdog timeout period. This action
typically initiates the processor's power-up routine. If the
interruption persists, new reset pulses are generated each
timeout period until RS is strobed. The timeout period is
typically 700msec.
It is often difficult to debug a system while the watchdog
is continuously generating reset pulses. For example, the
watchdog must be disabled when the system is operated
with an in-circuit emulator (ICE). The watchdog disable input
(TC70) is provided for system debugging, (or if the watchdog
timer on-board the processor is to be used). Grounding
WDD disables the watchdog (all other functions remain
intact). For normal watchdog operation, WDD can be tied to
V
DD
.
The software routine that drives the RS strobe must be
in a section of the program that executes frequently enough
so the time between toggles is less than one watchdog
timeout period. The strobe signal can be derived from
microprocessor address, data and/or control signals. Typi-
cal circuit examples are shown in Figure 1.
PIN DESCRIPTION
Pin No
Pin No
(TC70)
(TC71)
Symbol
Description
1
1
V
CCO
V
CC
Output. The higher of V
CC
or V
BATT
is internally switched to this output.
Connect to V
CC
if V
BATT
and V
CCO
are not used.
2
2
V
CC
V
CC
Input. +5V power supply.
3
3
GND
GND Input. Ground.
4
CEI
Chip enable input. Chip enable to static RAM or other device to be battery
backed-up. Connect to ground if V
CCO
is not used.
4
TDI
Threshold detector input. When the voltage on threshold detector input (TDI) is
less than 1.3V, threshold detector output (TDO) goes low.
5
CEO
Chip enable output. This line goes low only when CEI is low and V
CC
is above
the RESET threshold.
5
TDO
Threshold detector output. TDO goes low when TDI is less than 1.3V and V
CC
is
greater than V
BATT
. (The threshold detector is turned off when V
CC
is less than
V
BATT
.
6
WDD
Watchdog disable input. Grounding this line disables the watchdog timer (no
RESET pulses are generated after the watchdog timer times out). This input is
provided to facilitate system debug. This input is internally pulled-up and can be
left open, or tied to V
CC
for normal watchdog operation.
6
PF
Power fail output. This line goes low when V
CC
is below 4.5V nominal. It is used
to write-protect the external device to be battery backed.
7
7
RS
RESET/STORE (Bidirectional). An open drain with pull-up (in output mode) that
goes active if:
1. V
CC
falls below 4.5V nominal
2. If pulled low by an external electronic signal or switch closure
3. If the watchdog is not strobed within the minimum watchdog timeout period
4. During power-up and power down
In the input mode, RS is a negative edge triggered input that resets the
watchdog timer when pulled to ground through a 10k
, 5% tolerance resistor.
8
8
V
BATT
Backup battery input. Connect to ground if battery backup is not used.
DETAILED DESCRIPTION
Precision Power Supply Monitor
The RS pin is immediately driven low any time V
CC
is
below 4.5V nominal. The processor is held in its reset state
during power-up and power-down. RS remains low for a
minimum of 500msec after V
CC
is within tolerance to allow
the power supply and processor to stabilize.
Watchdog Timer
The processor drives the RS pin with an input/output
(I/O) line in series with a voltage divider to V
DD
. Pulling the
bottom of this divider low results in an internal voltage
change (strobe) sufficient to reset the watchdog timer, but
above the V
IL
input threshold of the processor RESET input.
The processor must continuously apply strobes in this
manner within a set period to verify proper software execu-
tion. A momentary reset (500msec minimum) is generated
if a hardware or software failure keeps RS from being
TC70
TC71
MICROMASTERTM SYSTEM SUPERVISOR
WITH POWER SUPPLY MONITOR, WATCHDOG
AND BATTERY BACKUP
5-11
TELCOM SEMICONDUCTOR, INC.
7
6
5
4
3
1
2
8
Figure 1. TC70 Typical Application
VCC
CE
WDD
VCCO
CEO
TC70
ADDRESS
DECODER
ADDRESS
CMOS
RAM
I/O
RESET
RESET
PROCESSOR
+5V
+3V L
I
BATTERY
R2
13K
R1
10K
+5V
VBATT
VCC
GND
CEI
RS
data corruption during power up and power down. The
battery switchover circuit compares V
CC
to the V
BATT
input
and connects VCCO to whichever is higher. Switchover
(V
SW
) occurs when V
CC
is 10mV below V
BATT
as V
CC
falls,
and when V
CC
is 10mV more than V
BATT
as V
CC
rises. The
battery switchover comparator has 20mV of hysteresis to
prevent switch chattering if V
CC
falls very slowly.
Integrated Battery Backup (TC71)
The TC71 differs from the TC70 in that it has a Power
Fail (PF) output instead of a gated chip enable (CEI, CEO).
PF must be externally gated with the decode for the CMOS
RAM or other device to be battery-backed. (Many CMOS
RAMs have both CE and CE enables. In this case, the PF
output can be connected directly to the CE input of the RAM).
PF is high as long as V
CC
is greater than 4.5V nominal.
When V
CC
falls below 4.5V nominal, PF is driven low.
Battery switchover for the TC71 is otherwise identical to that
of the TC70.
Supply Monitor Noise Sensitivity
The TC70/71 is optimized for fast response to negative-
going changes in V
DD
. Systems with an inordinate amount
of electrical noise on V
DD
(such as systems using relays),
may require a 0.1
F bypass capacitor to reduce detection
sensitivity. This capacitor should be installed as close to the
TC70/71 as possible to keep the capacitor lead length short.
TYPICAL APPLICATIONS
Figure 1 shows a full feature implementation of the
TC70; Figure 2 shows the TC71. Resistors R1 and R2 of
Figure 2 set the trip point voltage for the early power fail
warning circuit using the TC71 threshold detector.
Resistor Value Selection
The values of R1 and R2 must be chosen to ensure a
valid low strobe level (V
STL
) on RS when the processor I/O
line is low. The use of 10k
,
5% tolerance resistors are
recommended. These values result in a nominal strobe level
of 2.83V on RS (min/max of 2.43V/3.24V, assuming
V
DD
= 5.0V
10%). Other resistor values can be used, so
long as the additive tolerances of the power supply and
resistor values result in a strobe that falls within V
STH
and
V
STL
under all additive tolerance conditions.
External Override Reset Control
A built-in debounce circuit allows a pushbutton switch
(or other electronic reset signal) to be wire-ORed to RS as
an external reset override (Figure 4). The external reset
signal is required to be an active low signal of at least
20msec in duration. Internally, this input is timed to provide
a minimum reset pulse width output of 500msec.
Threshold Detector
The TC71 issues a low-true output on the TDO pin any
time the TDI pin is less than 1.3V and V
CC
is greater than
V
BATT
. The voltage to be monitored is connected to the TDI
input through a simple resistor divider. The threshold detec-
tor can be used to generate an early power fail warning if the
unregulated DC input to the +5V regulator is available for
monitoring.
Integrated Battery Backup (TC70)
The CEO line (TC70) drives the CE input of a CMOS
RAM or other device to be battery-backed. CEO follows CEI
as long as V
CC
is greater than 4.5V nominal. If V
CC
falls
below 4.5V nominal, CEO is driven to the potential of VCCO
thus write protecting the RAM and preventing accidental
TC70
TC71
MICROMASTERTM SYSTEM SUPERVISOR
WITH POWER SUPPLY MONITOR, WATCHDOG
AND BATTERY BACKUP
5-12
TELCOM SEMICONDUCTOR, INC.
TC70
TC71
Figure 4. RS Override Reset
Figure 3. Watchdog Strobe
Figure 2. TC71 Typical Application
VCC
CE
WDD
VCCO
PF
TC71
TC55RP
REGULATOR
FILTER CAP
ADDRESS
NMI
CMOS
RAM
I/O
RESET
RESET
PROCESSOR
3V L
I
R4
R3
VBATT
VCC
VCC
VCC
TDI
GND
CE
TDO
AC IN
RS
ADDRESS
DECODER
RECTIFIER
R4
13K
R3
10K
V
STL
(MAX)
t
ST
t
TD
RS
Note: t
TD
is the maximum elapsed time between strobes which
will keep the watchdog timer from forcing RS LOW.
(A
STROBE is defined as a high-to-low transition from V
STH
to V
STL
)
.
V
STH
(MIN)
V
STL
(MIN)
PB CLOSED
PB OPEN
RS
V
IH
t
RST
V
IL
tPBH
MICROMASTERTM SYSTEM SUPERVISOR
WITH POWER SUPPLY MONITOR, WATCHDOG
AND BATTERY BACKUP
5-13
TELCOM SEMICONDUCTOR, INC.
7
6
5
4
3
1
2
8
TC70
TC71
Figure 5. Power Up/Down Slew Rate
Figure 6. Power Up/Down Reset Timing
Figure 7. Battery Backup (Power-Up)
Figure 8. Battery Backup (Power-Down)
3.0V
4.25V
V
CC
tR
tF
RS
VOL
VOH
VCC
4.25V
tRST
tRPD
tPD
tR
VIH
VCC
VBATT- 0.2V
VIH
CEI
CEO
4.25V
3.0V
tF
tPD
VIL
VBATT-0.2V
VCC
CEI
4.25V
3.0V
CEO
MICROMASTERTM SYSTEM SUPERVISOR
WITH POWER SUPPLY MONITOR, WATCHDOG
AND BATTERY BACKUP