U2782B

TELEFUNKEN Semiconductors
Rev. A4, 17-Oct-97

1 (10)

1100 MHz Twin PLL

Description

The IC U2782B is a low power twin PLL manufactured
with TEMIC's advanced UHF process. The maximum
operating frequency is 1100 MHz for both PLLs.
It features a wide supply voltage range from 2.7 to 5.5 V.
Prescaler 64/65 and power down function for both PLL's
is integrated. Applications are CT1, IS54, JDC etc.

Electrostatic sensitive device.
Observe precautions for handling.

Features

D Very low current consumption (typical 3 V/11 mA)

D Supply voltage range 2.7 to 5.5 V
D Maximum input frequency: 1100 for both PLLs

D 2 pins for separate power down functions

D Output for PLL lock status
D Prescaler 64/65 for both inputs

D SSO20 package

D ESD protected according to MIL-STD 833

method 3015 cl.2

Benefits

D Low current consumption leads to extended talk time
D Twin PLL saves costs and space
D One foot print for all TEMIC twin PLL's saves design-

in time

Block Diagram

12 bit reference divider 2

12 bit latch 2

17 bit latch 2

17 bit main divider 2

17 bit

Shift register

17 bit latch 1

17 bit main divider 1

12 bit reference divider 1

12 bit latch 1

16 bit latch

Control functions

Oscillator

on / off

divide by 2

64 / 65 Prescaler 1

64 / 65 Prescaler 2

3 bit

Load control

Phase

detector 1

Phase

detector 2

Charge

pump 1

Charge

pump 2

Pump

bias

Lock

select

Ports

Power

down

Test

5I/Port 0

HPD1/Port1

HPD2/Port4

Port3

Lock Port2

CP1

Scp

Iset

CP2

analog

digital

DGND

AGND

OSCi

OSCo

RFi1

Clock

Data

Enable

RFi2

94 8916

Figure 1.

U2782B

TELEFUNKEN Semiconductors

Rev. A4, 17-Oct-97

2 (10)

Ordering Information

Extended Type Number

Package

Remarks

U2782B-AFS

SSO20

Rail, MOQ 830 PCS

U2782B-AFSG3

SSO20

Tape and Reel, MOQ 4000 pcs

Pin Description

20 Port 3

Iset

CP 2

Scp

RFi 2

GND

HPD2/Port 4

Enable

Data

Clock

5I/Port 0

digital

CP 1

analog

RFi 1

GND

OSC

HPD1/Port 1

Lock/Port 2

95 9622

Symbol

Function

5I/Port 0

5I � Control input / o.c.output

digital

Power supply digital section

CP 1

Charge pump output of
synthesizer 1

analog Power supply analog section

RFi 1

RF divider input synthesizer

GND

Ground for digital section

OSC

Reference oscillator input

OSC

Reference oscillator output

HPD 1/

Port 1

Hardware power down input of
synthesizer 1 / o.c.output

Lock/

Port 2

Lock output / o.c.output /
testmode output

Clock

3-wire-bus: serial clock input

Data

3-wire-bus: serial data input

Enable

3-wire-bus: serial enable input

HPD 2/

Port 4

Hardware power down input of
synthesizer 2 / o.c.output

GND

Ground for analog section

RFi 2

RF divider input synthesizer 2

Scp

Charge pump supply voltage

CP 2

Charge pump output of
synthesizer 2

Iset

Reference pin for charge pump
currents

Port 3

o.c.output

Absolute Maximum Ratings

Parameters

Symbol

Value

Unit

Supply voltage

Pins 2, 4 and 17

, V

Scp

Input voltage

Pins 1, 3, 5, 8, 9, 10, 11, 12, 13,

14, 15, 16, 18 and 20

0 to V

Junction temperature

125

�

Storage temperature range

stg

� 40 to + 125

�

Operating Range

Parameters

Symbol

Value

Unit

Supply voltage

Pins 2, 4 and 17

, V

Scp

2.7 to 5.5

Ambient temperature range

amb

� 40 to + 85

�

U2782B

TELEFUNKEN Semiconductors
Rev. A4, 17-Oct-97

3 (10)

Thermal Resistance

Parameters

Symbol

Value

Unit

Junction ambient

SSO20

thja

140

K/W

Electrical Characteristics

amb

= 25

_C, V

= 2.7 to 5.5 V, V

Scp

= 5 V, unless otherwise specified

Parameters

Test conditions

Symbol

Min.

Typ.

Max.

Unit

��

DC Supply

��

Supply current

��

= 3V, SPD1 = SPD2 = 0

��

0.5

��

0.8

��

1.1

��

Supply current

��

= 3V, SPD1 = SPD2 = 1

��

�

��

�

��

Supply current CP

��

�

��

�

��

= 5 V, PLL in lock

condition

��

�

��

�

��

�

��

�

��

�

��

�

��

�

��

�

��

�

��

�

��

�

PLL 1 + PLL2
Input voltage

RFi1

= 200 � 1100 MHz

RFi1

200

RMS

Scaling factor prescaler

PSC

64/65

Scaling factor main
counter

2047

Scaling factor swallow
counter

Reference counter

4096

Reference oscillator
Recommended crystal
series resistance

200

External reference input
frequency

AC coupled sinewave

RF/2 = 0
RF/2 = 1

OSC

1
1

20
40

MHz

External reference input
amplitude

AC coupled sinewave

OSC

100

RMS

Logic input levels (Clock, Data, Enable, HPD1, HPD2, 5I)
High input level

1.5

Low input level

0.4

High input current

�5

Low input current

�5

Logic output levels (Port 0, 1, 2, 3, 4, Lock)
Leakage current

= 5.5 V

Saturation voltage

= 0.5 mA

0.4

Charge pump output (R

set

= tbd.)

Source current

Scp

PLL2

5I = L

PLL1

5I = H

PLL1

source

� 1

�0.2

�1

Sink current

Scp

PLL2

5I = L

PLL1

5I = H

PLL1

sink

0.2

Leakage current

Scp

RMS voltage at 50

OSC

is open if an external reference frequency is applied

U2782B

TELEFUNKEN Semiconductors

Rev. A4, 17-Oct-97

4 (10)

Serial Bus Programming

Reference and programmable counters can be
programmed by the 3-wire-bus (Clock, Data and Enable).
After setting enable signal to high condition, the data sta-
tus is transfered but by but on the rising edge of the clock
signal into the shift register, starting with the MSB-bit.
After the Enable signal returns to low condition the
programmed information is loaded according to the
addressbits (last three bits) into the addressed latch.
Additional leading bits are ignored and there is no check
made how many clock pulses arrived during enable high
condition. In powerdown mode the 3-wire-bus remains
active and the IC can be programmed.

Data is entered with the most significant bit first. The
leading bits deliver the divider or control information.
The trailing three bits are the address field. There are six
different addresses used. The trailing address bits are
decoded upon the falling edge of the Enable signal. The
internal Loadpulse is beginning with the falling edge of
the Enable signal and ending with falling edge of the
Clock signal. Therefore a minimum holdtime clock-
enable t

HCE

is required.

Bit Allocation

MSB

LSB

Bit

data bits

address bits

D16 D15 D14 D13 D12

D11

D10

PLL1

M10

PLL1

R11

R10

PL1

PLL2

M10

PLL2

R11

R10

PLL2

RF/

Test

5IP

TRI

PS2

PS1

H2P H1P

LPA

D 5I

D 2

D 1

Scaling Factors

S0 ... S5:

These bits are setting the swallow counter S

= S0*2

+ S1*2

+ ... + S4*2

+ S5*2

allowed scalling factors for S

: 0 ... 63, T

< T

M0 ... M10: These bits are setting the main counter S

= M0*2

+ M1*2

+ ... + M9*2

+ M10*2

allowed scalling factors for S

: 5 ... 2047

PGD

: Total scalling factor of the programmable counter:

PGD

= (64*S

) + S

Condition: S

< S

R0 ... R11:

These bits are setting the reference counter S

= R0*2

+ ... + R10*2

+ R11*2

allowed scalling factors for S

: 5 ... 4096

RFD

: Total scalling factor of the reference counter:

RF/2 = 1:

RFD

= 2 * S

RF/2 = 0:

RFD

= S

U2782B

TELEFUNKEN Semiconductors
Rev. A4, 17-Oct-97

5 (10)

Serial Programming Bus

Control Bits:

P0 ... P4:

o.c. output ports (1 = high impedance)

LPA, LPB:

selection of P2 output or locksignal

LPA

LPB

function of pin 10

o.c. output P2

locksignal of synthesizer 2

locksignal of synthesizer 1

wiredor locksignal of both synthesizer

H1P, H2P:

selection of P1/4 output or hardware power down input of synthesizer 1/2 (0 = Port / 1 = HPD)

5IP:

selection of P0 output or high current switching input for the charge pump current of synthesizer 1

(0 = Port / 1 = charge pump 1 current switch input)

PS1, PS2:

phase selection of synthesizer 1 and synthesizer 2 (1 = normal / 0 = invers)

PS-PLL1/2 = 1

PS-PLL1/2 = 0

CP1/2

> f

sink

source

< f

source

sink

= f

RF/2: divide by 2 prescaler for reference divider (0 = off / 1 = on)

SPD1, SPD2: software power down bit of synthesizer 1/2 (0 = powerdown / 1 = powerup)

5I:

software switch for the charge pump current of synthesizer 1 (0 = low current / 1 = high current)

TRI1, TRI2: enables tristate for the charge pump of synthesizer 1/2 (0 = normal / 1 = tristate)

TEST: enables counter testmode (0 = disabled / 1 = enabled)

TEST

LPA

LPB

PS1

PS2

Testsignal

at pin 10

RFD1

PGD1

RFD2

PGD2

To operate the software power down mode the following condition must be set: HXP = 0; power up and power down
will be set by SPDX = 1 (on) and SPDX = 0 (off).
To operate the hardware power down mode the following condition must be set: HXP = 1; SPDX = 1; power up and
power down will be set by high and low state at the hardware power down pins 9/14.
High current of charge pump synthesizer 1 is active when 5I = 1 and if 5IP = 1 the charge pump current control input
pin 1 is in high state.

Электронный компонент: U2782B-AFS