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Электронный компонент: U4280BM-B

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U4280BM
Preliminary Information
TELEFUNKEN Semiconductors
Rev. A1, 10-Apr-97
1 (9)
AM / FM - PLL
Description
The U4280BM is an integrated circuit in BICMOS
technology for frequency synthesizer. It performs all the
functions of a PLL radio tuning system and is controlled
by I
2
C bus. The device is designed for all frequency
synthesizer applications of radio receivers, as well as
RDS (Radio Data System) applications.
Features
D Frequency range up to 150 MHz
D Pre-amplifier for AM and FM
D Fine tuning steps:
AM
y 1kHz
FM
y 2 kHz
D Two programmable 16-bit divider,
adjustable from 2 to 65535
D Reference oscillator up to 15 MHz
D 5 programmable switching outputs,
4 are open drain outputs up to 15 V
D Phase detector with separate outputs for AM and FM
D Controlled via I
2
C bus
Ordering Information
Extended Type Number
Package
Remarks
U4280BM-B
DIP20
U4280BM-BFL
SO20
Block Diagram
Shift register
Latch
Latch
I
2
C BUS
interface
AM / FM
switch
Preamplifier
N Divider
Analog
outputs
Preamplifier
: 2
Lock
detector
Current
sources
Phase
detector
Latch
Status
R Divider
Switching outputs
5
6
7
8
9
PRT
SWO1 SWO2 SWO3 AM/FM
14
13
16
17
15
PDFM
PDAM
PDFMO
PDAMO
LD
Oscillator
18
19
OSCOUT
2
3
4
SCL
SDA
AS
12
AMOSC
10
FMOSC
11
GND2
20
GND1
1
V
DD
13346
OSCIN
Figure 1. Block diagram
U4280BM
TELEFUNKEN Semiconductors
Rev. A1, 10-Apr-97
Preliminary Information
2 (9)
Pin Description
1
2
3
4
5
6
7
8
10
9
19
18
17
16
14
15
13
12
11
20
AS
PRT
13319
SWO1
SWO2
SWO3
AM/FM
SCL
SDA
LD
PDAMO
PDAM
PDFM
PDFMO
AMOSC
OSCOUT
OSCIN
FMOSC
GND
V
DD
GND
1
Figure 2. Pinning
Pin
Symbol
Function
1
V
DD
Supply voltage
2
SCL
I
2
C bus clock
3
SDA
I
2
C bus data
4
AS
Address selection
5
PRT
Switching port
6
SWO1
Switching output 1
7
SWO2
Switching output 2
8
SWO3
Switching output 3
9
AM/FM
Switching output AM/FM
10
FMOSC
FM oscillator input
11
GND2
Ground 2 (analog)
12
AMOSC
AM oscillator input
13
PDFMO
FM analog output
14
PDFM
FM current output
15
PDAM
AM current output
16
PDAMO
AM analog output
17
LD
Lock detect
18
OSCIN
Oscillator input
19
OSCOUT Oscillator output
20
GND1
Ground 1 (digital)
Functional Description
The U4280BM is controlled via the 2-wire I
2
C bus. For
programming there are one module address byte, two
subaddress bytes and five data bytes.
The module address contains a programmable address bit
A 1 which with address select input AS (Pin 4) makes it
possible to operate two U4280BM-B in one system. If bit
A 1 is identical with the status of the address select input
AS, the chip is selected.
The subaddress determines which one of the data bytes is
transmitted first. If subaddress of R-divider is
transmitted, the sequence of the next data bytes is DB 0
(Status), DB 1 and DB 2.
If subaddress of N-divider is transmitted, the sequence of
the next data bytes is DB 3 and DB 4. The bit organisation
of the module address, subaddress and 5 data bytes are
shown in figure 2
Each transmission on the I
2
C bus begins with the
"START "-condition and has to be ended by the "STOP"-
condition (see figure 3).
The integrated circuit U 4283 BM has two separate inputs
for AM and FM oscillator. Pre-amplified AM signal is
directed to the 16 bit N-divider via AM/FM switch,
whereas (pre-amplified) FM signal is first divided by a
fixed prescaler ( :2 ). AM/FM switch is controlled by
software. Tuning steps can be selected by 16 bit
R-divider. Further there is a digital memory phase
detector. There are two separate current sources for AM
and FM amplifier (charge pump) as given in electrical
characteristics. It allows independent adjustment of gain,
whereby providing high current for high speed tuning and
low current for stable tuning.
U4280BM
Preliminary Information
TELEFUNKEN Semiconductors
Rev. A1, 10-Apr-97
3 (9)
Bit Organization
MSB
LSB
Module address
1
1
0
0
1
0
0/1
0
A7
A6
A5
A4
A3
A2
A1
A0
Subaddress (R-divider)
X
X
X
X
0
1
X
X
Subaddress (N-divider)
X
X
X
X
1
1
X
X
MSB
LSB
Data byte 0 (Status)
PRT
SWO1
SWO2
SWO3
AM/
FM
PD
ANA
PD
POL
PD
CUR
D7
D6
D5
D4
D3
D2
D1
D0
Data byte 1
2
15
R-divider
2
8
Data byte 2
2
7
R-divider
2
0
Data byte 3
2
15
N-divider
2
8
Data byte 4
2
7
N-divider
2
0
LOW
HIGH
AM/FM
FM-operation
AM-operation
PD - ANA
PD analog
TEST
PD - POL
Negative polarity
Positive polarity
PD - CUR
Output current 2
Output current 1
Figure 3.
U4280BM
TELEFUNKEN Semiconductors
Rev. A1, 10-Apr-97
Preliminary Information
4 (9)
Transmission Protocol
MSB LSB
S
Address
A7 A0
A
Subaddress
R-divider
A
Data 0
A
Data 1
A
Data 2
A
P
MSB LSB
S
Address
A7 A0
A
Subaddress
N-divider
A
Data 3
A
Data 4
A
A
P
S = Start
P = Stop
A = Acknowledge
Figure 4.
Absolute Maximum Ratings
Parameters
Symbol
Value
Unit
Supply voltage
Pin 1
V
DD
0.3 to +6
V
Input voltages
Pins 2, 3, 4, 10, 12, 18 and 19
V
I
0.3 to V
DD
+ 0.3
V
Output currents
Pins 3, 5, 6, 7, 8 and 9
I
O
1 to +5
mA
Output drain voltage
Pins 6, 7, 8 and 9
V
OD
20
V
Ambient temperature range
T
amb
25 to +85
C
Storage temperature range
T
stg
40 to +125
C
Thermal Resistance
Parameters
Symbol
Value
Unit
Junction ambient
R
thJA
160
K/W
U4280BM
Preliminary Information
TELEFUNKEN Semiconductors
Rev. A1, 10-Apr-97
5 (9)
Electrical Characteristics
V
DD
= 5 V, T
amb
= 25
C, otherwise specified
Parameters
Test Conditions / Pins
Symbol
Min.
Typ.
Max.
Unit
Supply voltage range
Pin 1
V
DD
4.5
5.0
5.5
V
Quiescent supply voltage
Pin 1
I
DD
6.0
11.6
mA
FM input sensitivity
R
G
= 50
W
Pin 10
f
i
= 30 to 60 MHz
f
i
= 70 to 120 MHz
f
i
= 120 to 130 MHz
V
I
V
i
V
i
50
25
50
mV
mV
mV
AM input sensitivity
R
G
= 50
W
Pin 12
f
i
= 0.4 to 35 MHz
V
i
25
mV
Oscillator input sensitivity
R
G
= 50
W
Pin 18
f
i
= 0.1 to 15 MHz
V
i
100
mV
Adjustable divider
1)
2
65535
Switching output, PRT
Pin 5
I
H
= 1 mA
I
L
= 1 mA
I
L
= 0.1 mA
V
OH
V
OL
V
OL
V
DD
0.4
0.4
0.1
V
V
V
SWO1 to SWO3, AM/FM
(open drain outputs)
Pins 6 to 9
I
L
= 1 mA
I
L
= 0.1 mA
V
OL
V
OL
0.4
0.1
V
V
LD (open drain)
Pin 17
I
L
= 1 mA
V
OL
0.4
V
Phase detector
PDFM
Pin 14
Output current 1
Output current 2
I
O1
I
O2
400
100
500
125
600
150
mA
mA
PDAM
Pin 15
Output current 1
Output current 2
I
O1
I
O2
75
20
100
25
100
30
mA
mA
Analog output
Pins 14 and 15 to V
DD
Pins 14 and 15 to GND
I
13,16
I
13,16
0.1
1
0.5
2
mA
mA
I
2
bus inputs SCL, SDA
H input voltage, Pins 2 and 3
L input voltage, Pins 2 and 3
V
IH
V
IL
3
0
V
DD
1.5
V
V
Output voltage
I
SDAH
= 3 mA
V
O
0.4
V
Clock frequency
Pin 2
f
SCL
0
110
kHz
Bus timing
Rise time SCL, SDA
t
r
1
ms
Fall time SCL, SDA
t
f
300
ns
"H" phase SCL
t
H
4
ms
"L" phase SCL
t
L
4.7
ms
Waiting time START
t
wSTA
4
ms
Set up time START
t
hSTA
4
ms
Set up time STOP
t
sSTA
4.7
ms
Set up time DATA
t
sDAT
250
ns
Hold time DATA
t
hDAT
0
ms
1)
FM input frequency is additionally divided by two (Pin 10).