U6057B

Preliminary Information

TELEFUNKEN Semiconductors
Rev. A1, 03-Dec-97

1 (9)

Receiver for Point-to-Point Multiplex Systems

Description

Local, low speed multiplex systems reduce the amount of
wires and connectors, save costs and weight and increase
the safety in automotive and industrial applications. The
U6057B is an ideal receiver for an 8-bit data word with

simple protocol of a fixed length. It checks the correct
data transmission and provides the data word in an 8-bit
shift register for a microcontroller.

Features

D Only a single data line is necessary

D Quadruple comparison of the data signal for high

transmission safety

D Minimum of peripherals

D Master/slave operation
D Wide supply-voltage range
D According to VDE 0839
D Load-dump protected

Ordering Information

Extended Type Number

Package

Remarks

U6057B璅L

SO20

13273

Synchronization

Stabilization POR

Clock output

Oscillator

Operating
mode

Frequency divider

Start pulse

detection

Data decoding

Data end detection

Overflow store 8 bit

Buffer 8 bit

Sequence
control
detection

Safety condition

4-stage
counter

Comparison

Output memory
8-bit shift register

1. or 2. byte

Parallel
P

Serial
S

14 V

OSC

P/S

DIN

CLK

Stab

SYN

4/2

GND

DOUT

Figure 1. Block diagram

U6057B

TELEFUNKEN Semiconductors

Rev. A1, 03-Dec-97

Preliminary Information

2 (9)

Pin Configuration

Table 1. Pin description

Symbol

Function

GND

Ground

DIN

Serial data input

P/S

Parallel/serial switch-over

CLK

Clock input for shift register

DOUT

Serial data output for the

2/4

2/4-fold comparison

SYN

Synchronization

Clock output for cascading

Program pin

Data input of data line

OCS

RC-oscillator input

stab

Stabilized voltage

Supply voltage

P/S

CLK

13272

DOUT

2/4

DIN

Stab

OSC

SYN

GND

U6057B

Figure 2. Pinning of U6057B

Functional Description

Power Supply

For protection against interference and surges, the
U6057B must be equipped with an RC-circuit for current
limitation in the event of overvoltages and for buffering
in the event of voltage dips at V

Suggested dimensions: Rv = 510

W, C

= 100

(see figure 3 )

An integrated 14-V Z-diode is located between V

and

GND.

Oscillator

All timing in the circuit is derived from an RC-oscillator.
The oscillator's charging time t

is determined by an

external resistor, R

OSC

, and its discharge time t

by an

integrated 2-k

W resistor. Since the tolerance and

temperature sensitivity of the integrated resistor are
considerable greater than those of the external resistor,
t

20 must be selected for stability reasons. The

minimum value of R

OSC

should not be less than 68 k

Recommended frequencies and dimensioning:

OSC

= 1 / C

OSC

(0.79

OSC

+ 2260

OSC

= 25.6 kHz, C

OSC

= 220 pF, R

OSC

= 200 k

Table 2. Times derived from the transmitted frequency
(6.4 kHz)

Description

Time

Start pulse

312

One bit

156

Information bit

156

Zero bit

156

Information unit

625

Data word

5 ms + 312

ms start bit

Data pause

9.688 ms

Transmission cycle

15 ms

Minimum reaction time

60 ms

Data word master � slave

10 ms + 312

ms start bit

Data pause master � slave

4.688 ms

U6057B

Preliminary Information

TELEFUNKEN Semiconductors
Rev. A1, 03-Dec-97

3 (9)

Supply Voltage 5 V

The receivers can be supplied from one stabilized, noise-
free voltage source. In this case, the series resistor and the
filter capacitor are not required. Pin V

Stab

is also supplied

by the 5-V supply (see figure 4).

Structure of the Data Word

A switch information unit consists of four parts:

1. One bit for receiver synchronization

2. Information bit with "High" = switch open

"Low" = switch closed

3. Zero bit

4. Zero bit

The data word consists of two start bits and eight
information units. For a transmitter frequency of 6.4 kHz,
the data word length is 5 ms plus the start pulse followed
by a 10-ms-long data interval. The data interval has high
potential. When the supply voltage is applied, data
transmission is constantly repeated in accordance with
this pattern.

Data Decoding

If a negative edge appears at the data input, the receiver
checks whether a start pulse or a fault is present by
measuring the duration of the pulse (a minimum time
must be observed). If there is a fault, the receiver waits for
the next negative edge.

If it recognizes a start pulse, it checks whether an
information unit with 8 bits is following and stores this in
an 8-bit overflow store. The arriving data are ignored if
there is no 8-bit string owing to a fault or a synchronism.
The receiver is synchronized by each one bit. Scanning of
the information takes place in the middle of the
information bit. In order to make scanning sufficiently
precise, the oscillator frequency of the receiver was
selected to be four times as large as that of the transmitter.
The deviation of the receiver frequency to the four-fold
transmitter frequency may be up to

"15% while still

guaranteeing reliable data cognition.

Data Check

The data read into the 8-bit overflow store is compared
with the content of the buffer. If this is identical, a 4-stage
counter is incremented by one stage. If this is not
identical, the counter is reset. The new data combination
is transferred to the buffer after each comparison
irrespective of the result.

After double or quadruple coincidence has been estab-
lished, the content of the buffer is always transferred to
the output memory.

Since the period of data transmission is 15 ms this results
in a minimum delay time of 60 ms or 30 ms for detection
of a change of the data word. Faults on the data line and
switch bouncing may lead to an extension of the delay
time.

Precondition to transfer the data word into the output
memory: Input P/S must be in high potential.

Synchronization

Proper data transfer requires a synchronization between
the internal data processing and the microcontroller's
read-out frequency.
The U6057B provides a synchronization pulse (Pin SYN)
of t = 16

1/f

OSC

which triggers the microcontroller to

read-out data in the following time window of typically
2

15 ms or 4 15 ms. The synchronization is derived

from the positive edge of the internal transfer pulse. This
pulse causes the data transfer to the output shift register
after double/quadruple data word comparison.

The microcontroller reads the output shift register after
each synchronization pulse. In practise, the time delay for
data recognition varies depending on the event of data
signal change on the data line and the status of the internal
4-stage (or 2-stage) counter. This counter is 0 after each
synchronization pulse. With a programmed quadruple
comparison the data recognition time ranges from
4

15 ms to 7 15 ms whereas it may range from

15 ms to 3 15 ms in the case of the programmed

double comparison.

If the system is operated with multiple change of the data-
word during the comparison time (4

15 ms or

15 ms), the data recognition time may last longer

than mentioned above.

Note: In master � slave operation, each IC produces its

own synchronization pulse.

Cascading (Master � Slave Operation)

Determination of master or slave is defined by the con-
necting of the Pin PP:

Master/ alone:

PP open or PP to V

Slave:

PP to GND

In master mode, the oscillator is connected with R

OSC

and

OSC,

and the clock output is active. In slave mode, the

oscillator is blocked and must be activated by the clock
output of the master. The master recognizes the start-bit
and decodes the first eight information bits. The slave also

U6057B

TELEFUNKEN Semiconductors

Rev. A1, 03-Dec-97

Preliminary Information

4 (9)

recognizes the start-bit but decodes the second eight in-
formation bits.

There are several possibilities of cascading

D CLK and DOUT are always connected in parallel.

Each shift register can be read-out individually by a
separate P/S line (see figure 5 ).

D CLK and P/S are always connected in parallel.

DOUT

MASTER

and DOUT

SLAVE

are connected with

each other. The 16-bit data word can be read-out seri-
ally via DOUT

SLAVE

in one operation (see figure 6 )

D Combinations with U6052B and U6057B (see fig-

ure 7)

Loading and Reading-out the Shift Register

Loading and reading-out of data from the shift register is
controlled by the three inputs DIN, CLK and P/S.

Input P/S = high

parallel operation

No data can be read-out from the shift register.
Data which arrive via the data line are stored in
the shift register. Output DOUT is disabled (high
resistance).

Input P/S = low

serial operation

The information available at DIN is transferred
to the shift register by the positive edge of CLK
and advanced by one position by each further
positive edge. The data word appears at DOUT.

The maximum clock frequency is 40 kHz.

The eighth flip-flop is a master � slave flip-flop. The
information of the eighth flip-flop is transferred to the
slave with each negative edge from CLK and is available
at the output DOUT.

DIN, CLK and EN are high-resistance inputs and process
a switching threshold of approximate 1.8 V. DOUT is an
open-collector output.

Input 4/2

The number of comparisons can be defined by the wiring
configuration of input 4/2.

4-fold comparison: Input 4/2 open
2-fold comparison: Input 4/2 connected to V

100

OSC

Data input

13274

Processor

Batt

100

510

U6057B

P/S

CLK

DOUT

SYN

Figure 3. Supplied with battery voltage

100

OSC

Data input

13275

Processor

5 V

U6057B

P/S

CLK

DOUT

SYN

Figure 4. Supplied with a stabilized 5-V voltage

协谢械泻褌褉芯薪薪褘泄 泻芯屑锌芯薪械薪褌: U6057B

协谢械泻褌褉芯薪薪褘泄泻芯屑锌芯薪械薪褌: U6057B