U6083B
TELEFUNKEN Semiconductors
Rev. A1, 14-Feb-97
1 (8)
PWM Power Control with Interference Suppression
Description
The U6083B is a PWM IC in bipolar technology for the
control of an N-channel power MOSFET used as a high
side switch. The IC is ideal for use in the brightness con-
trol (dimming) of lamps e.g., in dashboard applications.
Features
D Pulse-width modulation up to 2 kHz clock frequency
D Protection against short circuit, load dump
overvoltage and reverse V
S
D Duty cycle 18 to 100% continuously
D Internally reduced pulse slope of lamp's voltage
D Interference and damage protection according to
VDE 0839 and ISO/TR 7637/1.
D Charge pump noise suppressed
D Ground wire breakage protection
Ordering Information
Extended Type Number
Package
Remarks
U6083B
DIP8
Block Diagram
Current monitoring
+ short circuit detection
Output
Charge
pump
RC oscillator
Duty cycle
range
18 ... 100%
Duty cycle
reduction
Control input
Voltage
monitoring
Slew rate
control
5
1
4
3
V
S
C
5
PWM
Logic
6
7
8
47 k
W
47 nF
R
sh
2
R
3
95 9753
V
Batt
150
W
C
3
C
2
C
1
GND
Ground
Figure 1. Block diagram with external circuit
U6083B
TELEFUNKEN Semiconductors
Rev. A1, 14-Feb-97
2 (8)
Pin Description
1
2
3
4
5
6
7
8
95 9944
V
S
GND
V
I
Osc
Output
Sense
2 V
S
Delay
Pin
Symbol
Function
1
V
S
Supply voltage V
S
2
GND
IC ground
3
V
I
Control input (duty cycle)
4
Osc
Oscillator
5
Delay
Short circuit protection delay
6
Sense
Current sensing
7
2 V
S
Voltage doubler
8
Output
Output
Functional Description
Pin 1, Supply Voltage, V
s
or V
Batt
Overvoltage Detection
Stage 1:
If overvoltages V
Batt
> 20 V (typ.) occur, the external
transistor is switched off and switched on again at
V
Batt
< 18.5 V (hysteresis).
Stage 2:
If V
Batt
> 28.5 V (typ), the voltage limitation of the IC is
reduced from V
S
= 26 V to 20 V. The gate of the external
transistor remains at the potential of the IC ground, thus
producing voltage sharing between FET and lamps in the
event of overvoltage pulses occuring (e.g., load dump).
The short-circuit protection is not in operation. At V
Batt
approx. < 23 V, the overvoltage detection stage 2 is
switched off. Thus during overvoltage detection stage 2
the lamp voltage V
lamp
is calculated to :
V
Lamp
= V
Batt
V
S
V
GS
V
S
= Supply voltage of the IC at overvoltage detection
stage 2
V
GS
= Gate source voltage of the FET
Undervoltage Detection
In the event of voltages of approximately V
Batt
< 5.0 V,
the external FET is switched off and the latch for short-
circuit detection is reset.
A hysteresis ensures that the FET is switched on again at
approximately V
Batt
5.4 V.
Pin 2, GND
Ground-Wire Breakage
To protect the FET in the case of ground-wire breakage,
a 1 M
W resistor between gate and source it is recom-
mended to provide proper switch-off conditions.
Pin 3, Control Input
The pulse width is controlled by means of an external
potentiometer (47 k
W). The characteristic (angle of rota-
tion/duty cycle) is linear. The duty cycle can be varied
from 18 to 100%. It is possible to further restrict the duty
cycle with the resistors R
1
and R
2
(see figure 3).
In order to reduce the power dissipation of the FET and
to increase the lifetime of the lamps, the IC automatically
reduces the maximum duty cycle at Pin 8 if the supply
voltage exceeds V
2
= 13 V. Pin 3 is protected against
short-circuit to V
Batt
and ground (V
Batt
x
16.5 V).
Pin 4, Oscillator
The oscillator determines the frequency of the output
voltage. This is defined by an external capacitor, C
2
. It is
charged with a constant current, I, until the upper
switching threshold is reached. A second current source
is then activated which taps a double current, 2
I, from
the charging current. The capacitor, C
2
, is thus discharged
at the current, I, until the lower switching threshold is
reached. The second source is then switched off again and
the procedure starts once more.
Example for Oscillator Frequency Calculation:
Switching thresholds
V
T100
= High switching threshold (100% duty cycle)
V
T100
= V
S
a
1
= (V
Batt
I
S
R
3
)
a
1
V
T<100
= High switching threshold (< 100% duty cycle)
V
T<100
= V
S
a
2
= (V
Batt
I
S
R
3
)
a
2
V
TL
= Low switching threshold
V
TL
= V
S
a
3
= (V
Batt
I
S
R
3
)
a
3
whereas
a
1
,
a
2
and
a
3
are fixed constant.
Calculation Example
The above mentioned threshold voltages are calculated
for the following values given in the data sheet.
V
Batt
= 12 V, I
S
= 4 mA, R
3
= 150
W ,
a
1
= 0.7,
a
2
= 0.67 and
a
3
= 0.28.
U6083B
TELEFUNKEN Semiconductors
Rev. A1, 14-Feb-97
3 (8)
V
T100
= (12 V 4 mA
150 W) 0.7 [ 8 V
V
T<100
= 11.4 V
0.67 = 7.6 V
V
TL
= 11.4 V
0.28 = 3.2 V
Oscillator Frequency
3 cases have to be distinguished
1)
f
1
for duty cycle = 100%, no slope reduction with
capacitor C
4
(see figure 3)
f
1
+
I
osc
2
(V
T100
* V
TL
)
C
2
, whereas C
2
+ 68 nF
I
osc
+ 45 mA
f
1
+ ... + 75 Hz
2)
f
2
for duty cycle < 100%, no slope reduction with
capacitor C
4
For a duty cycle of less than 100%, the oscillator
frequency, f, is as follows:
f
2
+
I
osc
2
V
T
t100
* V
TL
C
2
, whereas C
2
+ 68 nF
I
osc
+ 45 mA
f
2
+ ... + 69Hz
3)
f
3
with duty cycle < 100% with slope reduction
capacitor C
4
(see page 3 "Output Slope Control")
f
3
+
I
osc
2
(V
T
t100
* V
TL
)
C
2
) 2V
Batt
C
4
whereas C
2
+ 68 nF
I
osc
+ 45 mA
C
4
+ 1.8 nF
f
3
+ ... + 70 Hz
By selecting different values of C
2
and C
4
, it is possible
to have a range of oscillator frequency, f, from 10 to
2000 Hz as shown in the data sheet.
Output Slope Control
The slope of the lamp voltage is internally limited to
reduce radio interference, by limitation of the voltage
gain of the PWM comparator.
Thus the voltage rise on the lamp is proportional to the
oscillator voltage increase at the switchover time accord-
ing to the equation.
dV
8
/dt =
a
4
dV
4
/dt =
2
a
4
f
(
a
2
a
3
)
(V
Batt
I
S
R
3
)
when
f = 75 Hz, V
TX
= V
T < 100
and
a
4
= 63
we obtain
dV
8
/dt=2
63 75 Hz (0.670.28) (12 V4 mA 15 W)
= 42 V/ms
Via an external capacitor, C
4
, the slope can be further
reduced as follows:
dV
8
/dt = I
OSC
/(C
4
+ C
2
/
a
4
)
when
I
OSC
= 45
mA, C
4
= 1.8 nF, C
2
= 68 nF and
a
4
= 63
then dV
8
/dt = 45
mA/(1.8 nF + 68 nF/63) = 15.6 V/ms
To damp oscillation tendencies, a resistance of 100
W in
series with capacitance C
4
is recommended.
Interference Suppression
"On board" radio reception according to VDE 0879 part
3/4.81
Test conditions refering to figure 2.
Application circuit according to figure 1 or 3.
Load: nine 4-W lamps in parallel.
Duty cycle
= 18%
V
Batt
= 12 V
f
Osc
= 100 Hz
Figure 2. Voltage spectrum of on-board radio reception
Pins 5 and 6, Short-Circuit Protection and
Current Sensing,
1. Short-Circuit Detection and Time Delay, t
d
The lamp current is monitored by means of an external
shunt resistor. If the lamp current exceeds the threshold
for the short-circuit detection circuit (V
T2
90 mV), the
duty cycle is switched over to 100% and the capacitor C
5
is charged by a current source of I
ch
I
dis
. The external
FET is switched off after the cut-off threshold (V
T5
) is
reached. Renewed switching on of the FET is possible
only after a power-on reset. The current source, I
dis,
ensures that the capacitor C
5
is not charged by parasitic
currents.
U6083B
TELEFUNKEN Semiconductors
Rev. A1, 14-Feb-97
4 (8)
Time delay, t
d
, is as follows:
t
d
= C
5
V
T5
/ (I
ch
I
dis
)
With C
5
= 100 nF and V
T5
= 10.4 V, I
ch
=13
mA,
I
dis
= 3
mA, we have
t
d
= 100 nF
10.4 V/ (13 mA 3 mA)
t
d
= 104 ms
2. Current Limitation:
The lamp current is limited by a control amplifier to
protect the external power transistor. The voltage drop
across an external shunt resistor acts as the measured
variable. Current limitation takes place for a voltage drop
of V
T1
100
mV. Owing to the difference
V
T1
V
T2
10 mV, it is ensured that current limitation
occurs only when the short-circuit detection circuit has
responded.
After a power-on reset, the output is inactive for half an
oscillator cycle. During this time, the supply voltage
capacitor can be charged so that current limitation is guar-
anteed in the event of a short-circuit when the IC is
switched on for the first time.
Pins 7 and 8, Charge Pump and Output,
Output, Pin 8, is suitable for controlling a power
MOSFET. During the active integration phase, the supply
current of the operational amplifier is mainly supplied by
the capacitor C
3
(bootstrapping). In addition, a trickle
charge is generated by an integrated oscillator
(f
7
400 kHz) and a voltage doubler circuit. This
permits a gate voltage supply at a duty cycle of 100%.
Absolute Maximum Ratings
Parameters
Symbol
Value
Unit
Junction temperature
T
j
150
C
Ambient temperature range
T
amb
40 to +110
C
Storage temperature range
T
stg
55 to +125
C
Thermal Resistance
Parameters
Symbol
Value
Unit
Junction ambient
R
thJA
120
K/W
Electrical Characteristics
T
amb
= 40 to +110
C, V
Batt
= 9 to 16.5 V, (basic function is guaranteed between 6.0 V to 9.0 V) reference point ground,
unless otherwise specified (see figure 1). All other values refer to Pin GND (Pin 2).
Parameters
Test Conditions / Pins
Symbol
Min.
Typ.
Max.
Unit
Current consumption
Pin 1
I
S
7.9
mA
Supply voltage
Overvoltage detection,
stage 1
V
Batt
25
V
Stabilized voltage
I
S
= 10 mA
Pin 1
V
s
24.5
27.0
V
Battery undervoltage
detection
on
off
V
Batt
4.4
4.8
5.0
5.4
5.6
6.0
V
U6083B
TELEFUNKEN Semiconductors
Rev. A1, 14-Feb-97
5 (8)
Unit
Max.
Typ.
Min.
Symbol
Test Conditions / Pins
Parameters
Battery overvoltage detection
Stage 1:
on
off
V
Batt
18.3
16.7
20.0
18.5
21.7
20.3
V
Stage 2:
Detection stage 2
on
off
V
Batt
25.5
19.5
28.5
23.0
32.5
26.5
V
Stabilized voltage
I
S
= 30 mA Pin 1
V
s
18.5
20.0
21.5
V
Short-circuit protection Pin 6
Short-circuit current
limitation
V
T1
= V
S
V
6
V
T1
85
100
120
mV
Short-circuit detection
V
T2
= V
S
V
6
V
T2
75
90
105
mV
T2
S
6
V
T1
V
T2
3
10
30
Delay timer short circuit detection, V
Batt
= 12 V Pin 5
Switched off threshold
V
T5
= V
S
V
5
V
T5
10.2
10.4
10.6
V
Charge current
I
ch
13
mA
Discharge current
I
dis
3
mA
Capacitance current
I
5
= I
ch
I
dis
I
5
5
10
15
mA
Voltage doubler
Pin 7
Voltage
Duty cycle 100%
V
7
2 V
S
Oscillator frequency
f
7
280
400
520
kHz
Internal voltage limitation
I
7
= 5 mA
V
7
26
27.5
30.0
V
g
7
(whichever is lower)
7
V
S+14
V
S+15
V
S+16
Edge steepness
dv
8
/dt =
a
4
dV
4
/dt
dV
8
/dt
max
a
4
53
63
72
130
V/ms
Gate output Pin 8
Voltage
Low level
V
8
0.35
0.70
0.95
V
g
V
Batt
= 16.5 V
T
amb
= 110
C, R
3
= 150
W
8
1.5 *)
High level,
duty cycle 100%
V
8
V
7
Current
V
8
= Low level
I
8
1.0
mA
V
8
= High level, I
7
> | I
8
|
8
1.0
Duty cycle
Min: C
2
= 68 nF
Max: V
Batt
v 12.4 V
V
Batt
= 16.5 V, C
2
= 68 nF
t
p
/T
15
100
65
18
73
21
81
%
Oscillator
Frequency
Pin4
f
10
2000
Hz
Threshold cycle
Upper
V
8
+ High, a
1
+
V
T100
V
S
a
1
0.68
0.7
0.72
Upper
V
8
+ Low, a
2
+
V
T
t100
V
S
a
2
0.65
0.67
0.69
Lower
a
3
+
V
TL
V
S
a
3
0.26
0.28
0.3
Oscillator current
V
Batt
= 12 V
I
osc
34
45
54
mA
Frequency
C
4
open, C
2
= 68 nF
duty cycle = 50%
f
56
75
90
Hz
*)
Reference point is battery ground.
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