U6084B
TELEFUNKEN Semiconductors
Rev. A1, 14-Feb-97
1 (8)
PWM Power Control with Automatic Duty Cycle Reduction
Description
The U6084B is a bipolar technology PWM-IC designed
for the control of an N-channel power MOSFET used as
a high-side switch. The IC is ideal for use in the brightness
control (dimming) of lamps such as, in dashboard
applications. For a constant brightness the preselected
duty cycle can be reduced automatically as a function of
the supply voltage.
Features
D Pulse width modulation up to 2 kHz clock frequency
D Protection against short circuit, load-dump
overvoltage and reverse V
S
D Duty cycle 0 to 100 % continuously
D Output stage for power MOSFET
D Interference and damage protection according to
VDE 0839 and ISO/TR 7637/1.
D Charge pump noise suppressed
D Ground wire breakage protection
Ordering Information
Extended Type Number
Package
Remarks
U6084BFP
SO16
Block Diagram
Current monitoring
+ short circuit detection
Output
Charge
pump
RC oscillator
Duty cycle
range
0100%
Duty cycle
reduction
Control input
Short circuit
latch monitoring
Voltage
monitoring
Enable/
disable
9
11
16
6
3
V
S
4
C
5
PWM
Logic
C
2
C
1
12
13
14
C
3
47 nF
R
sh
1
R
3
150
W
2
95 9751
C
6
V
Batt
5
47 k
W
Ground
Figure 1. Block diagram with external circuit
U6084B
TELEFUNKEN Semiconductors
Rev. A1, 14-Feb-97
2 (8)
Pin Description
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
95 9754
GND
En / Dis
V
I
Reduct
Attenuation
Osc
NC
NC
V
S
NC
Output
2 V
S
Sense
Delay
NC
Latch
Pin
Symbol
Function
1
GND
IC ground
2
En / Dis
Enable/disable
3
V
I
Control input (duty cycle)
4
Reduct
Duty cycle reduction
5
NC
Attenuation
6
Osc
Oscillator
7
NC
Not connected
8
NC
Not connected
9
Latch
Status short circuit latch
10
NC
Not connected
11
Delay
Short circuit protection delay
12
Sense
Current sensing
13
2V
S
Voltage doubler
14
Output
Output
15
NC
Not connected
16
V
S
Supply voltage V
S
Functional Description
Pin1, GND
Ground-Wire Breakage
To protect the FET in the case of ground-wire breakage,
a 820 k
W resistor between gate and source it is recom-
mended to provide proper switch-off conditions.
Pin 2, Enable/Disable
The dimmer can be switched on or off with pin 2 indepen-
dently of the set duty cycle.
V
2
Function
Approx. >0.7 V or open
Disable
< 0.7 V or connected to Pin 1
Enable
Pin 3, Control Input
The pulse width is controlled by means of an external po-
tentiometer (47 k
W). The characteristic (angle of
rotation/duty cycle) is linear. The duty cycle can be varied
from 0 to 100%. It is possible to further restrict the duty
cycle with the resistors R
1
and R
2
(see figure 2).
Pin 3 is protected against short-circuit to V
Batt
and ground
GND (V
Batt
x
16.5 V).
Pin 4, Duty Cycle Reduction
With Pin 4 connected according to figure 2, the set duty
cycle is reduced as from V
Batt
12.5 V. This causes a
power reduction in the FET and in the lamps. In addition,
the brightness of the lamps is largely independent of the
supply voltage range, V
Batt
= 12.5 to 16 V.
Output Slope Control
The rise and fall time (t
r
, t
f
) of the lamp voltage can be
limited to reduce radio interference. This is done with an
integrator which controls a power MOSFET as source fol-
lower. The slope time is controlled by an external
capacitor C4 and the oscillator current (see figure 2).
Calculation:
t
f
+ t
r
+ V
Batt
C
4
I
osc
With V
Batt
= 12 V, C
4
= 470 pF and I
osc
= 40
m A,we thus
obtain a controlled slope of
t
f
+ t
r
+ 12 V
470 pF
40
mA +
141
ms
Pin 5, Attenuation
Capacitor C
4
connected to Pin 5 damps oscillation
tendencies.
Pin 6, Oscillator
The oscillator determines the frequency of the output
voltage. This is defined by an external capacitor, C
2
. It is
U6084B
TELEFUNKEN Semiconductors
Rev. A1, 14-Feb-97
3 (8)
charged with a constant current, I, until the upper switch-
ing threshold is reached. A second current source is then
activated which taps a double current, 2
I, from the
charging current. The capacitor, C
2
, is thus discharged by
the current, I, until the lower switching threshold is
reached. The second source is then switched off again and
the procedure starts once more.
Example for Oscillator Frequency Calculation
V
T100
+ V
S
a
1
+ (V
Batt
* I
S
R
3
)
a
1
V
T
100
+ V
S
a
2
+ (V
Batt
* I
S
R
3
)
a
2
V
TL
+ V
S
a
3
+ (V
Batt
* I
S
R
3
)
a
3
where
V
T100
+ High switching threshold (100% duty cycle)
V
T
t100
+ High switching threshold (t 100% duty cycle)
V
TL
+ Low switching threshold
a
1
,
a
2
and
a
3
are fixed constant.
The above mentioned threshold voltages are calculated
for the following values given in the data sheet.
V
Batt
= 12 V, I
S
= 4 mA, R
3
= 150
W ,
a
1
= 0.7,
a
2
= 0.67 and
a
3
= 0.28.
V
T100
+ (12 V * 4 mA 150 W ) 0.7 [ 8 V
V
T
t100
+ 11.4 V 0.67 + 7.6 V
V
TL
+ 11.4 V 0.28 + 3.2 V
For a duty cycle of 100%, an oscillator frequency, f, is
as follows:
f
+
I
osc
2
(V
T100
* V
TL
)
C
2
, where C
2
+ 22 nF
and
I
osc
+ 40 mA
Therefore:
f
+
40
mA
2
(8 V * 3.2 V) 22 nF +
189 Hz
For a duty cycle of less than 100%, the oscillator fre-
quency, f, is as follows:
f
+
I
osc
2
(V
T
t100
* V
TL
)
C
2
) 4 V
Batt
C
4
whereas
C
4
= 470 pF
+
40
m
A
2
7.6 V * 3.2 V 22 nF ) 4 12 V 470 pF
+ 185 Hz
A selection of different values of C
2
and C
4
, provides a
range of oscillator frequency, f, from 10 to 2000 Hz.
Pins 7, 8, 10 and 15
Not connected.
Pin 9, Status Short Circuit Latch
The status of the short-circuit latch can be monitored via
Pin 9 (open collector output).
Pin 9
Function
L
Short-circuit detected
H
No short-circuit detected
Pins 11 and 12, Short-Circuit Protection
and Current Sensing
1. Short-Circuit Detection and Time Delay, t
d
The lamp current is monitored by means of an external
shunt resistor. If the lamp current exceeds the threshold
for the short-circuit detection circuit (V
T2
90 mV), the
duty cycle is switched over to 100% and the capacitor C
5
is charged by a current source of 20
m A (I
ch
I
dis
). The
external FET is switched off after the cut-off threshold
(V
T11
) is reached. Renewed switching on the FET is pos-
sible only after a power-on reset. The current source, I
dis,
ensures that the capacitor C
5
is not charged by parasitic
currents. The capacitor C
5
is discharged by I
dis
to typ.
0.7 V.
Time delay, t
d
, is as follows:
t
d
+ C
5
@ (V
T11
* 0.7 V) (I
ch
* I
dis
)
With C
5
= 330 nF and V
Batt
= 12 V, we have
t
d
+ 330 nF @ (9.8 V * 0.7 V) 20 mA
+ 150 ms.
U6084B
TELEFUNKEN Semiconductors
Rev. A1, 14-Feb-97
4 (8)
2. Current Limitation
The lamp current is limited by a control amplifier that
protects the external power transistor. The voltage drop
across an external shunt resistor acts as the measured vari-
able. Current limitation takes place for a voltage drop of
V
T1
100
mV. Owing to the difference
V
T1
V
T2
10 mV, current limitation occurs only when
the short-circuit detection circuit has responded.
After a power-on reset, the output is inactive for half an
oscillator cycle. During this time , the supply voltage ca-
pacitor can be charged so that current limitation is
guaranteed in the event of a short circuit when the IC is
switched on for the first time.
Pins 13 and 14, Charge Pump and Output
Output, Pin 14, is suitable for controlling a power MOS-
FET. During the active integration phase, the supply
current of the operational amplifier is mainly supplied by
the capacitor C
3
(bootstrapping). Additionally, a trickle
charge is generated by an integrated oscillator
(f
13
400 kHz) and a voltage doubler circuit. This per-
mits a gate voltage supply at a duty cycle of 100%.
Pin 16, Supply Voltage, V
s
or V
Batt
Undervoltage Detection:
In the event of voltages of approx. V
Batt
< 5.0 V, the ex-
ternal FET is switched off and the latch for short-circuit
detection is reset.
A hysteresis ensures that the FET is switched on again at
approximately V
Batt
5.4 V.
Overvoltage Detection
Stage 1
If overvoltages V
Batt
> 20 V (typ.) occur, the external
transistor is switched off and switched on again at
V
Batt
< 18.5 V (hysteresis).
Stage 2
If V
Batt
> 28.5 V (typ.), the voltage limitation of the IC
is reduced from 26 V to 20 V. The gate of the external
transistor remains at the potential of the IC ground, thus
producing voltage sharing between FET and lamps in the
event of overvoltage pulses occuring (e.g., load-dump).
The short-circuit protection is not in operation. At
V
Batt
<
23
V, the overvoltage detection stage 2 is
switched off.
Absolute Maximum Ratings
Parameters
Symbol
Value
Unit
Junction temperature
T
j
150
C
Ambient temperature range
T
amb
40 to +110
C
Storage temperature range
T
stg
55 to +125
C
Thermal Resistance
Parameters
Symbol
Value
Unit
Junction ambient
R
thJA
120
K/W
Electrical Characteristics
T
amb
= 40 to +110
C, V
Batt
= 9 to 16.5 V, (basic function is guaranteed between 6.0 V to 9.0 V) reference point ground,
unless otherwise specified (see figure 1). All other values refer to Pin GND (Pin 1).
Parameters
Test Conditions / Pins
Symbol
Min.
Typ.
Max.
Unit
Current consumption
Pin 16
I
S
6.8
mA
Supply voltage
Overvoltage detection,
stage 1
V
Batt
25
V
Stabilized voltage
I
S
= 10 mA
Pin 16
V
S
24.5
27.0
V
Battery undervoltage
detection
on
off
V
Batt
4.4
4.8
5.0
5.4
5.6
6.0
V
U6084B
TELEFUNKEN Semiconductors
Rev. A1, 14-Feb-97
5 (8)
Unit
Max.
Typ.
Min.
Symbol
Test Conditions / Pins
Parameters
Battery overvoltage detection Pin 2
Stage 1:
on
off
V
Batt
18.3
16.7
20.0
18.5
21.7
20.3
V
Stage 2:
on
off
V
Batt
25.5
19.5
28.5
23.0
32.5
26.5
V
Stabilized voltage
I
S
= 30 mA Pin 16
V
Z
18.5
20.0
21.5
V
Short-circuit protection Pin 12
Short-circuit current limita-
tion
V
T1
= V
S
V
12
V
T1
85
100
120
mV
Short-circuit detection
V
T2
= V
S
V
12
V
T2
75
90
105
mV
T2
S
12
V
T1
V
T2
3
10
30
mV
Delay timer short circuit detection Pin 11
Switched off threshold
V
T11
= V
S
V
11
V
T11
9.5
9.8
10.1
V
Charge current
I
ch
23
mA
Dicharge current
I
dis
3
mA
Capacitance current
I
5
= I
ch
I
dis
I
5
13
20
27
mA
Output short-circuit latch Pin 9
Saturation voltage
I
9
= 100
mA
V
sat
150
350
mV
Voltage doubler
Pin 13
Voltage
Duty cycle 100%
V
13
2 V
S
Oscillator frequency
f
13
280
400
520
kHz
Internal voltage limitation
I
13
= 5 mA
V
13
26
27.5
30.0
V
g
(whichever is lower)
V
13
(V
S+14
)
(V
S+15
)
(V
S+16
)
Gate output
Pin 14
Voltage
Low level
V
14
0.35
0.70
0.95
V
g
V
Batt
= 16.5 V,
T
amb
= 110
C, R
3
= 150
W
14
1.5 *)
High level,
duty cycle 100%
V
14
V
13
Current
V
14
= Low level
I
14
1.0
mA
V
14
= High level, I
13
> | I
14
|
14
1.0
Enable/ Disable Pin 2
Current
V
2
= 0 V
I
2
20
40
60
mA
Duty cycle reduction Pin 4
Z-voltage
I
4
= 500
mA
V
4
6.9
7.4
8.0
V
Oscillator
Frequency
Pin6
f
10
2000
Hz
Threshold cycle
Upper
V
14
+ High, a
1
+
V
T100
V
S
a
1
0.68
0.7
0.72
V
14
+ Low, a
2
+
V
T
t100
V
S
a
2
0.65
0.67
0.69
Lower
a
3
+
V
TL
V
S
a
3
0.26
0.28
0.3
Oscillator current
V
Batt
= 12 V
I
osc
26
40
54
mA
Frequency tolerance
C
4
open, C
2
= 470 nF,
duty cycle = 50%
f
6.0
9.9
13.5
Hz
*)
Reference point is battery ground.
PDF 
ZIP