U6209B
Preliminary Information
TELEFUNKEN Semiconductors
Rev. A2, 30-Aug-96
1 (11)
1.3 GHz PLL for TV- and VCR- Tuner
Description
The U6209B is a single chip PLL frequency synthesizer
with unidirectional I
2
C-bus control. This IC contains a
high frequency prescaler which can be switched off.
Five open collector switching outputs are available. The
U6209B has a programmable 512/1024 reference divider.
Features
D 1.3 GHz divide-by-8 prescaler integrated
(can be bypassed)
D 15 bit counter accepts input frequencies up to
170 MHz
D Programmable reference divider: divider by 512 or
1024
D mP-controlled by I
2
C-Bus (MC44818 data format
compatible)
D Five port outputs (open collector )
D Four addresses selectable at Pin 10 for multi-tuner
application
D 31.25 kHz ( 1.3 GHz ) / 3.90625 kHz ( 170 MHz )
tuning steps with 4MHz Xtal
D Electrostatic protection according to MILSTD 883
D SO16 small package
Block Diagram
P3
P0
P1
I C Bus
Control
SCL
SDA
5-bit latch
Switching
Outputs
5-bit latch
8-bit latch
7-bit latch
15-bit latch
PD
15-bit counter
RFi
Phase
Detector
Charge
Pump
VD
512 / 1024
Osc.
6
8
4
5
1
14
13
16
12
15
2
3
Vs
Prescaler
GND
Crystal
Gate
PSC
T1
OS
T0 5I
2
7
9
11
P4
P2
AS 10
1 OR 8
RD1,2
FPRD
FRFD
95 10750
Figure 1.
Ordering Information
Extended Type Number
Package
Remarks
U6209B-GFPG3
SO16 plastic package
Taped and reeled
U6209B
TELEFUNKEN Semiconductors
Rev. A2, 30-Aug-96
Preliminary Information
2 (11)
Pin Configuration
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PD
Q1
Q2
SDA
95 10758
SCL
P3
P2
P1
RFi
RFi
V
S
P4
AS
P0
GND
VD
Figure 2.
Pin
Symbol
Function
1
PD
Charge pump output
2
Q1
Crystal
3
Q2
Crystal
4
SDA
Data in/output
5
SCL
Clock
6
P3
Port output (open collector)
7
P2
Port output (open collector)
8
P1
Port output (open collector)
9
P0
Port output (open collector)
10
AS
Address select input
11
P4
Port output (open collector)
12
Vs
Supply voltage
13
RFi
RF input
14
RFi
RF input
15
GND
Ground
16
VD
Active filter output
Circuit Description
The U6209B is a single-chip PLL designed for TV and
VCR receiver systems. It consists of a bridgeable
divide-by-8 prescaler with an integrated preamplifier, a
15-bit programmable divider, a crystal oscillator and a
reference divider with two selectable divider ratios
(512 / 1024), and a phase/frequency detector together
with a charge pump which drives the tuning amplifier.
Only one external transistor is required for varactor-line
driving. The device can be controlled via I
2
C bus format.
There are four programmable addresses selectable,
programmed by applying a specific input voltage to the
address-select input, enabling the use of up to four
synthesizers in a system. Five open collector output port
functions are included which are capable of sinking at
least 10 mA.
Oscillator frequency calculation:
fvco = PSF x SF x frefosc / 1024
fvco: Locked frequency of voltage controlled oscillator
PSF : Scaling factor of prescaler (1 or 8)
SF :
Scaling factor of programmable 15-bit divider
frefosc :Reference oscillator frequency:
3.2/4 MHz crystal or external reference frequency
In addition, there are port outputs available for band-
switching and other purposes.
Application
A typical application is shown on page 10. All input /
output interface circuits are shown on page 9.
Some special features which are related to test- and
alignment procedures for tuner production are explained
together within the following I
2
C bus mode description.
U6209B
Preliminary Information
TELEFUNKEN Semiconductors
Rev. A2, 30-Aug-96
3 (11)
Absolute Maximum Ratings
All voltages are referred to GND (Pin 15).
Parameters
Symbol
Min.
Typ.
Max.
Unit
Supply voltage
Pin 12
V
S
0.3
6
V
RF input voltage
Pins 13,14
RFi
0.3
V
S
+ 0.3
V
Crystal input voltage
Pin 2
Q1
0.3
V
S
+ 0.3
V
Charge pump output voltage
Pin 1
PD
0.3
V
S
+ 0.3
V
Active filter output voltage
Pin 16
VD
0.3
V
S
+ 0.3
V
Bus input/ output voltage
Pin 4
Pin 5
VSDA
VSCL
0.3
0.3
6
6
V
V
SDA output current
open collector Pin 4
ISDA
1
5
mA
Address select voltage
Pin 10
VAS
0.3
V
S
+ 0.3
V
Port output current open collector
Pins 69,11
P04
1
15
mA
Total port output current open collector Pins 69,11
P04
1
50
mA
Port output voltage in off state
In ON state
Pins 69,11
P04
0.3
0.3
15
6
V
V
Junction temperature
Tj
40
125
C
Storage temperature
Tstg
40
125
C
Operating Range
All voltages are referred to GND (Pin 15).
Parameters
Test Conditions / Pins
Symbol
Min.
Typ.
Max.
Unit
Supply voltage
Pin 12
Vs
4.5
5.5
V
Ambient temperature
T
amb
0
70
C
Input frequency
PSC = 1
Pins 13,14
RFi
64
1300
MHz
Input frequency
PSC = 0
Pins 13,14
RFi
1
170
MHz
Programmable divider
SF
256
32767
Crystal oscillator
Pin 2
fXTAL
3
4
4.48
MHz
Thermal Resistance
Parameters
Symbol
Value
Unit
SO16 small package
R
thJA
110
K/W
U6209B
TELEFUNKEN Semiconductors
Rev. A2, 30-Aug-96
Preliminary Information
4 (11)
Electrical Characteristics
Test Conditions (unless otherwise specified) : V
S
= 5V, T
amb
= 25
C.
Parameters
Test Conditions / Pins
Symbol
Min.
Typ.
Max.
Unit
Supply current
(prescaler ON)
SW 04 = 0; PSC =1
Pin 12
Is
32
42
52
mA
(prescaler OFF)
SW 04 = 0; PSC =0
Pin 12
Is
22
28
35
mA
Input sensitivity
fi = 80 - 1000 MHz
PSC = 1
Pin 13
Vi 1)
10
315
mVrms
fi = 1300 MHz
PSC = 1
Pin 13
Vi 1)
40
315
mVrms
fi = 10 - 170 MHz
PSC = 0
Pin 13
Vi 1)
10
315
mVrms
Port outputs
(open collector)
P04
Pins 69, 11
Leakage current
VH = 13.5 V
IL
10
uA
Saturation voltage
IL = 10 mA
VSL 2)
0.5
V
Charge pump output (PD)
Charge pump current `H'
5I = 1, VPD = 2 V
Pin 1
IPDH
180
uA
Charge pump current `L'
5I = 0, VPD = 2 V
Pin 1
IPDL
50
uA
Charge pump leakage
current
T0 = 0, VPD = 2 V Pin 1
IPDTRI
5
nA
Charge pump amplifier
gain
Pins 1, 16
6400
Bus inputs (SDA,SCL)
Input voltage high
Pins 4, 5
Vi `H'
3
5.5
V
Input voltage low
Pins 4, 5
Vi `L'
1.5
V
Input current high
Vi `H' = V
S
Pins 4, 5
Ii `H'
10
uA
Input current low
Vi `L' = 0 V Pins 4, 5
Ii `L'
20
uA
Output voltage SDA
(open collector)
ISDA `L' = 2 mA
Pin 4
VSDA `L'
0.4
V
Address selection input (AS)
Input current high
Input current low
VAS "H" = V
S
Pin
8
VAS "L" = 0 V
Pin 8
IiAS "H"
IiAS "L"
100
10
uA
Notes:
1)
RMS-voltage calculated from the measured available power on 50
W
2)
Tested with one switch active
U6209B
Preliminary Information
TELEFUNKEN Semiconductors
Rev. A2, 30-Aug-96
5 (11)
Functional Description
The U6209B is programmed via a 2wire I
2
C bus data
format. The three bus input Pins 4, 5, 10 are used as SDA,
SCL and address select inputs. The data includes the
scaling factor SF (15 bit) and port output information.
There are some additional functions included for testing
of the device.
I
2
C - Bus Description
The U6209B is controlled via a 2-wire I
2
C bus format by
feeding data and clock signals into the SDA and SCL lines
respectively. The table `I
2
CBUS DATA FORMAT'
describes the format of the data and shows how to select
the device address by applying a voltage at pin 10. When
the correct address byte has been received, the SDA line
is pulled low by the device during the acknowledge
period, and then also during the acknowledge periods,
when additional data bytes are programmed. After the
address transmission (first byte), data bytes can be sent to
the device. There are four data bytes requested to fully
program the device. The programmable divider latch is
loaded after the 8th clock pulse of the second divider byte
PDB2, the control and the port register latches are loaded
after the 8th clock pulse of the control byte CB1 respec-
tively post byte CB2. The table `I
2
C-BUS PULSE
DIAGRAM' shows some possible data transfer exam-
ples.
The programmable divider bytes PDB1 and PDB2 are
stored in a 15-bit latch and control the division ratio of the
15-bit programmable divider. The control Byte CB1
enables the control of the the following special functions:
D 5I-bit switches between low and high charge pump
current
D T1-bit enables divider test mode when it is set to
logic 1
D T0-bit enables the charge pump to be disabled when
it is set to logic 1
D RD1 and RD2-bit allow selection of the reference
divider ratio
D PSCbit switches prescaler off when it is set to
logic 0
D OS-bit disables the charge pump drive amplifier out-
put when it is set to logic 1.
When T1 is set to logic 1, the programmable divider out-
put signal is switched to pin 7 and the reference divider
output signal is switched to pin 6. The OS-bit function
disables the complete PLL function. This enables tuner
alignment by supplying the tuning voltage directly via the
30-V supply voltage of the tuner. The control byte CB2
programs the port outputs P0-4; a logic 0 for high
impedance output (off) and a logic 1 for low impedance
output (on).
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