THAT Corporation 1240 Series Datasheet

THAT Corporation; 45 Sumner Street; Milford, Massachusetts 01757-1656; USA

Tel: +1 (508) 478-9200; Fax: +1 (508) 478-0990; Web: www.thatcorp.com

600035 Rev 00

T H A T

C o r p o r a t i o n

THAT 1240, 1243, 1246

FEATURES

· High CMRR: typ. 90dB at 60Hz
· Excellent audio performance

Wide bandwidth: typ. >24 MHz

High slew rate: typ. 12 V/

Low distortion: typ. 0.0006 % THD

Low noise: typ. -103 dBu (re: input)

· Low current: typ. 2 mA
· Several gains: 0 dB, ±3 dB, & ±6 dB
· Industry-standard pinout

APPLICATIONS

· Balanced Audio Line Receivers

· Instrumentation Amplifiers

· Differential Amplifiers

· Precision Summers

· Current Shunt Monitors

Description

The THAT 1240-series of precision differential

amplifiers was designed primarily for use as bal-
anced line receivers for audio applications. Gains
of 0 db,

±3 dB, and ±6 dB are available to suit var-

ious applications requirements.

These devices are laser trimmed in wafer form

to obtain the precision resistor matching needed
for high CMR performance and precise gain. Man-
ufactured in THAT Corporation's proprietary com-
plementary dielectric isolation (DI) process, the
THAT 1240-series provides the sonic benefits of
discrete designs with the simplicity, reliability,

matching, and small size of a fully integrated solu-
tion.

All three versions of the part typically exhibit

90dB of common-mode rejection. With 12 V/

slew rate, >24MHz bandwidth, and 0.0006% THD,
these devices are sonically transparent. Moreover,
current consumption is typically a low 2 mA. Both
surface-mount and DIP packages are available.

The THAT 1246 is pin-compatible with the TI

INA137 and Analog Devices SSM2143, while the
THAT 1240 is pin-compatible with the SSM2141.

Sense

Vout

Ref

Vcc

Vee

In+

In-

Gain

R , R

9 k

10.5 k

12 k

R , R

9 k

7.5 k

6 k

Part no.

THAT1240

THAT1243

THAT1246

0 dB

-3 dB

-6 dB

Figure 1. THAT1240-series equivalent circuit diagram

Gain

Plastic DIP

Plastic SO

0 dB

1240P

1240S

-3 dB

1243P

1243S

-6 dB

1246P

1246S

Table 2. Ordering information

Pin Name

DIP Pin

SO Pin

Ref

In-

In+

Vee

Sense

Vout

Vcc

Table 1. 1240 Series pin assignments

Balanced Line Receiver ICs

THAT Corporation; 45 Sumner Street; Milford, Massachusetts 01757-1656; USA

Tel: +1 (508) 478-9200; Fax: +1 (508) 478-0990; Web: www.thatcorp.com

Page 2

THAT 1240 Series

Balanced Line Receiver ICs

SPECIFICATIONS

Absolute Maximum Ratings

Positive Supply Voltage (V

)

+20 V

Negative Supply Voltage (V

)

-20 V

Storage Temperature Range (T

)

-40 to +125°C

Output Short-Circuit Duration (t

)

Continuous

Input Voltages (In+, In-)

±50 V

Power Dissipation (P

) (T

= 85°C)

400 mW (DIP)

Power Dissipation (P

) (T

= 85°C)

260 mW (SO)

Operating Temperature Range (T

)

0 to 85°C

Junction Temperature (T

)

125°C

Lead Temperature (Soldering 10 seconds)

300 °C

Electrical Characteristics

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Supply Current

No signal

2.0

2.8

Supply Voltage

+18

-3

-18

Input Voltage Range

IN-DIFF

Differential (equal and opposite swing)

THAT 1240 (0 dB gain)

21.5

dBu

THAT 1243 (-3 dB gain)

24.4

dBu

THAT 1246 (-6 dB gain)

27.5

dBu

IN-CM

Common mode

THAT 1240 (0 dB gain)

27.5

dBu

THAT 1243 (-3 dB gain)

29.1

dBu

THAT 1246 (-6 dB gain)

31.5

dBu

Input Impedance

IN-CM

Common mode (all versions)

IN-DIFF

Differential

THAT 1240 (0 dB gain)

THAT 1243 (-3 dB gain)

THAT 1246 (-6 dB gain)

Common Mode Rejection Ratio

CMRR

Matched source impedances; V

= ±10 V

60 Hz

20 kHz

Power Supply Rejection Ratio

PSR

at 60 Hz, with V

= -V

THAT 1240 (0 dB gain)

THAT 1243 (-3 dB gain)

THAT 1246 (-6 dB gain)

Total Harmonic Distortion

THD

IN-DIFF

= 10V; BW = 20 kHz;

f = 1 kHz, R

= 2 k

0.0006

Small Signal Bandwidth

-3dB

= 2 k

W; C

= 10 pf

THAT 1240 (0 dB gain)

MHz

THAT 1243 (-3 dB gain)

MHz

THAT 1246 (-6 dB gain)

MHz

= 2 k

W; C

= 300 pf

THAT 1240 (0 dB gain)

MHz

THAT 1243 (-3 dB gain)

MHz

THAT 1246 (-6 dB gain)

MHz

Document 600035 Rev. 00

Page 3

THAT Corporation; 45 Sumner Street; Milford, Massachusetts 01757-1656; USA

Tel: +1 (508) 478-9200; Fax: +1 (508) 478-0990; Web: www.thatcorp.com

Output Noise

(OUT)

22 Hz to 22 kHz bandwidth

THAT 1240 (0 dB gain)

-103

dBu

THAT 1243 (-3 dB gain)

-105

dBu

THAT 1246 (-6 dB gain)

-106

dBu

Slew Rate

= 2 k

W; C

= 300 pf

Output Gain Error

ER(OUT)

f = 1 kHz

-0.05

+0.05

Output Voltage Swing

O+

= 2 k

- 2.5

-2

O+

= 2 k

+ 2 V

+ 2.5

Output Offset Voltage

OFF

No signal

-7

Output Short Circuit Current

= 0

±25

Resistive Load

Capacitive Load

300

Package Characteristics

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Through-hole Package

Type

See Figure 14, Page 10 for dimensions

8-Pin PDIP

Thermal Resistance

DIP package soldered to board

100

ºC/W

Surface Mount Package

Type

See Figure 15, Page 10 for dimensions

8-Pin SOP

Thermal Resistance

SO package soldered to board

150

ºC/W

Soldering Reflow Profile

JEDEC JESD22-A113-B (220 ºC)

All specifications are subject to change without notice.

Unless otherwise noted, T

=25°C, V

= +15V, V

= -15V, Test circuit is as shown in Figure 2.

0 dBu = 0.775Vrms.

While specific resistor ratios are very closely trimmed, absolute resistance values can vary ±25% from the

typical values shown. Input impedance is monitored by lot sampling.

Defined with respect to differential gain.

Theory of Operation

The THAT1240-series ICs consist of high perfor-

mance opamps with integrated, laser-trimmed resis-
tors. These designs take full advantage of THAT's
fully complementary dielectric isolation (DI) process
to deliver excellent performance with low current
consumption.

The devices are simple to apply in

many applications.

Resistor Trimming, Values, and CMRR

The 1240-series devices rely upon proprietary,

laser-trimmed, silicon-chromium (Si-Cr), thin-film,
integrated resistors to deliver the precise matching
required to achieve a 90dB common mode rejection
ratio. Trimming is performed in two cycles, both us-
ing dc inputs.

First, gain is set by trimming the

pair. Then, CMRR is set by trimming the other

pair (R

). Generally, only one resistor of each pair

is trimmed (whichever needs to increase to meet the
required specification).

To achieve 90 dB CMRR, the R

ratio is

trimmed to within ±0.005 % of the R

ratio.

Since the resistors themselves are on the order of
10 k

W (see Figure 1 for actual values, which change

with the specific part), an increase of as little as
0.6

W can reduce the CMRR from over 90 dB to only

84 dB. The better the starting CMRR, the more im-
pact (in dB) a given added resistance will have.

Therefore, to achieve this high CMRR in practice,

care should be taken to ensure that all source im-
pedances remain balanced.

To accomplish this,

PCB traces carrying signal should be balanced in

length, connector resistance should be minimized,
and any input capacitance (including strays) should
be balanced between the + and - legs of the input
circuitry. Note that the additional contact resistance
of some sockets is sufficient to undo the effects of
precision trimming. Therefore, socketing the parts
is not recommended. THAT's 1200-series InGenius

input stages address many of these difficulties
through a patented method of increasing com-
mon-mode input impedance.

A further consideration is that after trimming,

the two resistor divider ratios are tightly controlled,
but the actual value of any individual resistor is not.
In fact, two of the four resistors are normally left
without trimming. The initial tolerance of the resis-
tors is quite wide, so it is possible for any given re-
sistor to vary over a surprisingly wide range,
Lot-to-lot variations of up to ±25 % are to be ex-
pected.

Input Considerations

The 1240-series devices are internally protected

against input overload via an unusual arrangement
of diodes connecting the + and - Input pins to the
power supply pins. The circuit of Figure 3 shows the
arrangement used for the R

/ R

side; a similar one

applies to the other side. The zener diodes prevent
the protection network from conducting until an in-
put pin is raised at least 50 V above V

or below

. Thus, the protection networks protect the de-

vices without constraining the allowable signal swing
at the input pins. The reference (and sense) pins are

THAT Corporation; 45 Sumner Street; Milford, Massachusetts 01757-1656; USA

Tel: +1 (508) 478-9200; Fax: +1 (508) 478-0990; Web: www.thatcorp.com

Page 4

THAT 1240 Series

Balanced Line Receiver ICs

Sense

Vout

Ref

IN(CM)

In+

In-

½v

IN(DIFF)

½v

IN(DIFF)

Figure 2. THAT1240 series test circuit

protected via more conventional reverse-biased di-
odes which will conduct if these pins are raised
above V

or below V

Because the 1240-series devices are input stages,

their input pins are of necessity connected to the
outside world. This is likely to expose the parts to
ESD when cables are connected and disconnected.
Our testing indicates that the 1240-series devices
will typically withstand application of up to 1,000
volts under the human body ESD model.

To reduce risk of damage from ESD, and to pre-

vent RF from reaching the devices, THAT recom-
mends the circuit of Figure 4. C

through C

should

be located close to the point where the input signal
comes into the chassis, preferably directly on the
connector. The unusual circuit design is intended to
minimize the unbalancing impact of differences in
the values of C

and C

by forcing the capacitance

from each input to chassis ground to depend pri-
marily on the value of C

. The circuit shown is ap-

proximately ten times less sensitive to mismatches
between C

and C

than the more conventional ap-

proach, in which the junction of C

and C

grounded directly. An excellent discussion of input
stage grounding can be found in the June 1995 is-
sue of the Journal of the Audio Engineering Society,
Vol. 43, No. 6, in articles by Stephen Macatee, Bill
Whitlock, and others.

Note that, because of the tight matching of the in-

ternal resistor ratios, coupled with the uncertainty
in absolute value of any individual resistor, RF by-
passing through the addition of R-C networks at the
inputs (series resistor followed by a capacitor to
ground at each input) is not recommended.

The

added resistors can interact with the internal ones
in unexpected ways. If some impedance for the
RF-bypass capacitor to work against is deemed nec-
essary, THAT recommends the use of a ferrite bead
or balun instead.

If it is necessary to ac-couple the inputs of the

1240-series parts, the coupling capacitors should be
sized to present negligible impedance at any fre-
quencies of interest for common mode rejection. Re-
gardless of the type of coupling capacitor chosen,
variations in the values of the two capacitors, work-
ing against the 1240-series input impedance (itself
subject to potential imbalances in absolute value,
even when trimmed for perfect ratio match), can un-
balance common mode input signals, converting
them to balanced signals which will not be rejected
by the CMRR of the devices. For this reason, THAT
recommends

dc-coupling

the

inputs

the

1240-series devices.

Input Voltage Limitations

When configured, respectively, for -3 dB and

-6 dB gain, the 1243 and 1246 devices are capable
of accepting input signals above the power supply
rails.

This is because the internal opamp's inputs

connect to the outside world only through the
on-chip resistors R

through R

at nodes a and b as

shown in Figure 2. Consider the following analysis.

Differential Input Signals

For differential signals (v

IN(DIFF)

), the limitation to

signal handling will be output clipping. The outputs
of all the devices typically clip at within 2V of the
supply rails. Therefore, maximum differential input
signal levels are directly related to the gain and sup-
ply rails.

THAT Corporation; 45 Sumner Street; Milford, Massachusetts 01757-1656; USA

Tel: +1 (508) 478-9200; Fax: +1 (508) 478-0990; Web: www.thatcorp.com

Document 600035 Rev. 00

Page 5

In+

Ref

Figure 3. Representative Input Protection Circuit

C4
470p

470p

47p

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