54AC11109, 74AC11109
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS450 MARCH 1987 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Copyright
1993, Texas Instruments Incorporated
21
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin V
CC
and GND Configurations
Minimize High-Speed Switching Noise
EPIC
TM
(Enhanced-Performance Implanted
CMOS) 1-
m Process
500-mA Typical Latch-Up Immunity
at 125
C
ESD Protection Exceeds 2000 V,
MIL STD-883C Method 3015
Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
description
These devices contain two independent J-K
positive-edge-triggered flip-flops. A low level at
the preset (PRE) or clear (CLR) inputs sets or
resets the outputs regardless of the levels of the
other inputs. When preset and clear are inactive
(high), data at the J and K inputs meeting the setup
time requirements are transferred to the outputs
on the positive-going edge of the clock pulse.
Clock triggering occurs at a voltage level and is not
directly related to the rise time of the clock pulse.
Following the hold time interval, data at the J and
K inputs may be changed without affecting the
levels at the outputs. These versatile flip-flops can
perform as toggle flip-flops by grounding K and
tying J high. They also can perform as D-type
flip-flops by tying the J and K inputs together.
The 54AC11109 is characterized for operation over the full military temperature range of 55
C to 125
C. The
74AC11109 is characterized for operation from 40
C to 85
C.
FUNCTION TABLE
(each gate)
INPUTS
OUTPUTS
PRE
CLR
CLK
J
K
Q
Q
L
H
X
X
X
H
L
H
L
X
X
X
L
H
L
L
X
X
X
H
H
H
H
L
L
L
H
H
H
H
L
Toggle
H
H
L
H
Q0
Q0
H
H
H
H
H
L
H
H
L
X
X
Q0
Q0
This configuration is nonstable; that is, it will not persist when
either PRE or CLR returns to its inactive (high) level.
54AC11109 . . . J PACKAGE
74AC11109 . . . D OR N PACKAGE
(TOP VIEW)
54AC11109 . . . FK PACKAGE
(TOP VIEW)
NC No internal connection
1PRE
1Q
1Q
GND
2Q
2Q
2PRE
2CLK
1CLK
1K
1J
1CLR
V
CC
2CLR
2J
2K
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
2J
2K
NC
2CLK
2PRE
1K
1CLK
NC
1PRE
1Q
1J
NC
2Q
2Q
2CLR
1Q
GND
NC
V
1CLR
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
54AC11109, 74AC11109
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS450 MARCH 1987 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
22
logic symbol
C1
3
5
2
6
S
1
1J
14
16
1K
15
R
13
S
7
2J
10
8
2K
9
R
11
1PRE
1J
1K
1CLK
1CLR
2PRE
2J
2K
2CLK
2CLR
1Q
1Q
2Q
2Q
C2
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
100 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
54AC11109, 74AC11109
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS450 MARCH 1987 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
23
recommended operating conditions
54AC11109
74AC11109
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
VCC
Supply voltage
3
5
5.5
3
5
5.5
V
VCC = 3 V
2.1
2.1
VIH
High-level input voltage
VCC = 4.5 V
3.15
3.15
V
VCC = 5.5 V
3.85
3.85
VCC = 3 V
0.9
0.9
VIL
Low-level input voltage
VCC = 4.5 V
1.35
1.35
V
VCC = 5.5 V
1.65
1.65
VI
Input voltage
0
VCC
0
VCC
V
VO
Output voltage
0
VCC
0
VCC
V
VCC = 3 V
4
4
IOH
High-level output current
VCC = 4.5 V
24
24
mA
VCC = 5.5 V
24
24
VCC = 3 V
12
12
IOL
Low-level output current
VCC = 4.5 V
24
24
mA
VCC = 5.5 V
24
24
t /
v
Input transition rise or fall rate
0
10
0
10
ns / V
TA
Operating free-air temperature
55
125
40
85
C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
54AC11109
74AC11109
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
3 V
2.9
2.9
2.9
IOH = 50
A
4.5 V
4.4
4.4
4.4
5.5 V
5.4
5.4
5.4
VOH
IOH = 4 mA
3 V
2.58
2.4
2.48
V
VOH
I
24
A
4.5 V
3.94
3.7
3.8
V
IOH = 24 mA
5.5 V
4.94
4.7
4.8
IOH = 50 mA
5.5 V
3.85
IOH = 75 mA
5.5 V
3.85
3 V
0.1
0.1
0.1
IOL = 50
A
4.5 V
0.1
0.1
0.1
5.5 V
0.1
0.1
0.1
VOL
IOL = 12 mA
3 V
0.36
0.5
0.44
V
VOL
IOL = 24 mA
4.5 V
0.36
0.5
0.44
V
IOL = 24 mA
5.5 V
0.36
0.5
0.44
IOL = 50 mA
5.5 V
1.65
IOL = 75 mA
5.5 V
1.65
II
VI = VCC or GND
5.5 V
0.1
1
1
A
ICC
VI = VCC or GND,
IO = 0
5.5 V
4
80
40
A
Ci
VI = VCC or GND
5 V
3.5
pF
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
54AC11109, 74AC11109
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS450 MARCH 1987 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
24
timing requirements, V
CC
= 3.3 V
0.3 V (see Figure 1)
TA = 25
C
54AC11109
74AC11109
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
0
70
0
70
0
70
MHz
t
Pulse duration
PRE or CLR low
5
5
5
ns
tw
Pulse duration
CLK low or CLK high
7.2
7.2
7.2
ns
t
Setup time before CLK
Data high or low
5.5
5.5
5.5
ns
tsu
Setup time before CLK
PRE or CLR inactive
2.5
2.5
2.5
ns
th
Hold time after CLK
0
0
0
ns
timing requirements, V
CC
= 5 V
0.5 V (see Figure 1)
TA = 25
C
54AC11109
74AC11109
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
0
100
0
100
0
100
MHz
t
Pulse duration
PRE or CLR low
4
4
4
ns
tw
Pulse duration
CLK low or CLK high
5
5
5
ns
t
Setup time before CLK
Data high or low
4.5
4.5
2.5
ns
tsu
Setup time, before CLK
PRE or CLR inactive
2
2
2
ns
th
Hold time, after CLK
0
0
0
ns
switching characteristics over recommended operating free-air temperature range,
V
CC
= 3.3 V
0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25
C
54AC11109
74AC11109
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
fmax
70
100
70
70
MHz
tPLH
PRE or CLR
Q or Q
1.5
6.5
9
1.5
10.5
1.5
9.9
ns
tPHL
PRE or CLR
Q or Q
1.5
8
12.6
1.5
14.4
1.5
13.7
ns
tPLH
CLK
Q or Q
1.5
8
11.4
1.5
13.5
1.5
12.7
ns
tPHL
CLK
Q or Q
1.5
7.5
10.5
1.5
12.7
1.5
11.8
ns
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25
C
54AC11109
74AC11109
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
fmax
100
125
100
100
MHz
tPLH
PRE or CLR
Q or Q
1.5
4.5
6.5
1.5
7.6
1.5
7.1
ns
tPHL
PRE or CLR
Q or Q
1.5
5
8.6
1.5
10.2
1.5
9.6
ns
tPLH
CLK
Q or Q
1.5
5.5
7.9
1.5
9.4
1.5
8.8
ns
tPHL
CLK
Q or Q
1.5
5
7.3
1.5
8.6
1.5
8.1
ns
operating characteristics, V
CC
= 5 V, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Cpd
Power dissipation capacitance per gate
CL = 50 pF, f = 1 MHz
32
pF
54AC11109, 74AC11109
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS450 MARCH 1987 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
25
PARAMETER MEASUREMENT INFORMATION
50% VCC
50%
50%
50%
VCC
VCC
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
50%
50%
VCC
0 V
50% VCC
50% VCC
Input
(see Note B)
Out-of-Phase
Output
In-Phase
Output
Timing Input
(see Note B)
50% VCC
VOLTAGE WAVEFORMS
VCC
0 V
50%
50%
tw
VOLTAGE WAVEFORMS
Input
LOAD CIRCUIT
From Output
Under Test
CL = 50 pF
(see Note A)
500
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr = 3 ns, tf = 3 ns.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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