54ACT11109, 74ACT11109
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS451 FEBRUARY 1987 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Copyright
1993, Texas Instruments Incorporated
21
Inputs Are TTL-Voltage Compatible
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin V
CC
and GND Configurations
Minimize High-Speed Switching Noise
EPIC
TM
(Enhanced-Performance Implanted
CMOS) 1-
m Process
500-mA Typical Latch-Up Immunity
at 125
C
Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and
Ceramic 300-mil DIPs
description
These devices contain two independent J-K
positive-edge-triggered flip-flops. A low level at
the preset (1PRE or 2PRE) or clear (1CLR or
2CLR) input sets or resets the outputs regardless
of the levels of the other inputs. When PRE and
CLR are inactive (high), data at the J and K inputs
meeting the setup time requirements are
transferred to the outputs on the positive-going
edge of the clock pulse. Clock triggering occurs at
a voltage level and is not directly related to the rise
time of the clock pulse. Following the hold-time
interval, data at the J and K inputs may be
changed without affecting the levels at the
outputs. These versatile flip-flops can perform as
toggle flip-flops by grounding K and tying J high.
They also can perform as D-type flip-flops if J and
K are tied together.
The 54ACT11109 is characterized for operation over the full military temperature range of 55
C to 125
C. The
74ACT11109 is characterized for operation from 40
C to 85
C.
FUNCTION TABLE
INPUTS
OUTPUTS
PRE
CLR
CLK
J
K
Q
Q
L
H
X
X
X
H
L
H
L
X
X
X
L
H
L
L
X
X
X
H
H
H
H
L
L
L
H
H
H
H
L
Toggle
H
H
L
H
Q0
Q0
H
H
H
H
H
L
H
H
L
X
X
Q0
Q0
This configuration is nonstable; that is, it will not persist when
either PRE or CLR returns to the inactive (high) level.
54ACT11109 . . . J PACKAGE
74ACT11109 . . . D OR N PACKAGE
(TOP VIEW)
54ACT11109 . . . FK PACKAGE
(TOP VIEW)
NC No internal connection
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1PRE
1Q
1Q
GND
2Q
2Q
2PRE
2CLK
1CLK
1K
1J
1CLR
V
CC
2CLR
2J
2K
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
2J
2K
NC
2CLK
2PRE
1K
1CLK
NC
1PRE
1Q
1J
NC
2Q
2Q
2CLR
1Q
GND
NC
CC
V
1CLR
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
54ACT11109, 74ACT11109
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS451 FEBRUARY 1987 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
22
logic symbol
S
1
1J
14
1J
16
1CLK
C1
3
1Q
2
1K
15
R
13
7
10
2J
8
2CLK
5
2Q
6
9
11
1PRE
2PRE
1CLR
1K
2CLR
2K
1Q
2Q
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
100 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
recommended operating conditions
54ACT11109
74ACT11109
UNIT
MIN
MAX
MIN
MAX
UNIT
VCC
Supply voltage
4.5
5.5
4.5
5.5
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
VI
Input voltage
0
VCC
0
VCC
V
VO
Output voltage
0
VCC
0
VCC
V
IOH
High-level output current
24
24
mA
IOL
Low-level output current
24
24
mA
t /
v
Input transition rise or fall rate
0
10
0
10
ns/ V
TA
Operating free-air temperature
55
125
40
85
C
54ACT11109, 74ACT11109
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS451 FEBRUARY 1987 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
23
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
54ACT11109
74ACT11109
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
IOH = 50
A
4.5 V
4.4
4.4
4.4
IOH = 50
A
5.5 V
5.4
5.4
5.4
VOH
IOH = 24 mA
4.5 V
3.94
3.7
3.8
V
VOH
IOH = 24 mA
5.5 V
4.94
4.7
4.8
V
IOH = 50 mA
5.5 V
3.85
IOH = 75 mA
5.5 V
3.85
IOL = 50
A
4.5 V
0.1
0.1
0.1
IOL = 50
A
5.5 V
0.1
0.1
0.1
VOL
IOL = 24 mA
4.5 V
0.36
0.5
0.44
V
VOL
IOL = 24 mA
5.5 V
0.36
0.5
0.44
V
IOL = 50 mA
5.5 V
1.65
IOL = 75 mA
5.5 V
1.65
II
VI = VCC or GND
5.5 V
0.1
1
1
A
ICC
VI = VCC or GND,
IO = 0
5.5 V
4
80
40
A
ICC
One input at 3.4 V,
Other inputs at VCC or GND
5.5 V
0.9
1
1
mA
Ci
VI = VCC or GND
5 V
3.5
pF
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
timing requirements over recommended operating free-air temperature range, V
CC
= 5 V
0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25
C
54ACT11109
74ACT11109
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
0
100
0
100
0
100
MHz
t
Pulse duration
PRE or CLR low
5.5
5.5
5.5
ns
tw
Pulse duration
CLK high or low
5
5
5
ns
t
Setup time before CLK
Data high or low
5.5
5.5
5.5
ns
tsu
Setup time before CLK
PRE or CLR inactive
2
2
2
ns
th
Hold time, data after CLK
0
0
0
ns
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25
C
54ACT11109
74ACT11109
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
fmax
100
125
100
100
MHz
tPLH
PRE or CLR
Q or Q
1.5
5.5
8.6
1.5
9.8
1.5
9.2
ns
tPHL
PRE or CLR
Q or Q
1.5
6
10.8
1.5
12.6
1.5
11.8
ns
tPLH
CLK
Q or Q
1.5
6
8.3
1.5
9.7
1.5
9.1
ns
tPHL
CLK
Q or Q
1.5
5.5
7.6
1.5
9
1.5
8.3
ns
54ACT11109, 74ACT11109
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS451 FEBRUARY 1987 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
24
operating characteristics, V
CC
= 5 V, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Cpd
Power dissipation capacitance per flip-flop
CL = 50 pF, f = 1 MHz
31
pF
PARAMETER MEASUREMENT INFORMATION
50% VCC
1.5 V
1.5 V
1.5 V
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
1.5 V
1.5 V
3 V
0 V
50% VCC
50% VCC
Input
(see Note B)
Out-of-Phase
Output
In-Phase
Output
Timing Input
(see Note B)
50% VCC
VOLTAGE WAVEFORMS
3 V
0 V
1.5 V
1.5 V
tw
VOLTAGE WAVEFORMS
Input
LOAD CIRCUIT
From Output
Under Test
CL = 50 pF
(see Note A)
500
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr = 3 ns, tf = 3 ns.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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pertaining to warranty, patent infringement, and limitation of liability.
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accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL
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Copyright
1998, Texas Instruments Incorporated
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