54ACT11821, 74ACT11821
10-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS156A NOVEMBER 1990 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Copyright
1993, Texas Instruments Incorporated
21
Inputs Are TTL-Voltage Compatible
Provides Extra Data Width Necessary for
Wider Address/Data Paths or Buses With
Parity
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin V
CC
and GND Configurations
Minimize High-Speed Switching Noise
EPIC
TM
(Enhanced-Performance Implanted
CMOS) 1-
m Process
500-mA Typical Latch-Up Immunity at 125
C
Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Ceramic 300-mil
DIPs
description
These 10-bit flip-flops feature 3-state outputs
designed specifically for driving highly-capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing wider buffer
registers, I/O ports, bidirectional bus drivers with
parity, and working registers.
On the positive transition of the clock the Q outputs
will follow the D inputs.
A buffered output enable (OE) input can be used
to place the ten outputs in either a normal logic
state (high or low level) or a high-impedance state.
In the high-impedance state the outputs neither
load nor drive the bus lines significantly.
The high-impedance state and increased drive
provide the capability to drive the bus lines in a
bus-organized system without need for interface
or pull-up components.
The output enable (OE)does not affect the internal operation of the flip-flops. Old data can be retained or new
data can be entered while the outputs are in the high-impedance state.
The 54ACT11821 is characterized for operation over the full military temperature range of 55
C to 125
C. The
74ACT11821 is characterized for operation form 40
C to 85
C.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
EPIC is a trademark of Texas Instruments Incorporated.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1Q
2Q
3Q
4Q
5Q
GND
GND
GND
GND
6Q
7Q
8Q
9Q
10Q
OE
1D
2D
3D
4D
5D
V
CC
V
CC
6D
7D
8D
9D
10D
CLK
54ACT11821 . . . JT PACKAGE
74ACT11821 . . . DW PACKAGE
3 2 1
13 14
5
6
7
8
9
10
11
8D
9D
10
CLK
10Q
9Q
8Q
2D
1D
OE
1Q
2Q
3Q
4Q
4
15 16 17 18
GND
GND
GND
GND
6Q
7Q
3D
4D
5D
V
54ACT11821 . . . FK PACKAGE
(TOP VIEW)
28 27 26
25
24
23
22
21
20
19
12
5Q
V
6D
7D
(TOP VIEW)
CC
CC
54ACT11821, 74ACT11821
10-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS156A NOVEMBER 1990 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
22
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
OE
CLK
D
Q
L
H
H
L
L
L
L
L
X
Q0
L
H
X
Q0
L
X
X0
H
X
X
Z
logic symbol
logic diagram (positive logic)
8D
7D
6D
5D
4D
3D
2D
1D
CLK
OE
18
19
20
23
24
25
26
27
15
28
8Q
7Q
6Q
5Q
4Q
3Q
2Q
1Q
12
11
10
5
4
3
2
1
1D
C1
EN
8D
7D
6D
5D
4D
3D
2D
1D
CLK
OE
18
19
20
23
24
25
26
27
15
28
8Q
7Q
6Q
5Q
4Q
3Q
2Q
1Q
12
11
10
5
4
3
2
1
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
9D
17
9Q
13
10D
16
10Q
14
Pin numbers shown are for the DW, JT, and NT packages.
10D
9D
16
17
10Q
9Q
14
13
1D
C1
1D
C1
54ACT11821, 74ACT11821
10-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS156A NOVEMBER 1990 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
23
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
250 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
55
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
recommended operating conditions (see Note 2)
54ACT11821
74ACT11821
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
VCC
Supply voltage
4.5
5
5.5
4.5
5
5.5
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
VI
Input voltage
0
VCC
0
VCC
V
VO
Output voltage
0
VCC
0
VCC
V
IOH
High-level output current
24
24
mA
IOL
Low-level output current
24
24
mA
t /
v
Input transition rise or fall rate
0
10
10
ns / V
TA
Operating free-air temperature
55
125
40
85
C
NOTE 2: Unused or floating inputs must be held high or low.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
54ACT11821, 74ACT11821
10-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS156A NOVEMBER 1990 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
24
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
54ACT11821
74ACT11821
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
IOH = 50
A
4.5 V
4.4
4.4
4.4
IOH = 50
A
5.5 V
5.4
5.4
5.4
VOH
IOH = 24 mA
4.5 V
3.94
3.7
3.8
V
VOH
IOH = 24 mA
5.5 V
4.94
4.7
4.8
V
IOH = 50 mA
5.5 V
3.85
IOH = 75 mA
5.5 V
3.85
IOL = 50
A
4.5 V
0.1
0.1
0.1
IOL = 50
A
5.5 V
0.1
0.1
0.1
VOL
IOL = 24 mA
4.5 V
0.36
0.5
0.44
V
VOL
IOL = 24 mA
5.5 V
0.36
0.5
0.44
V
IOL = 50 mA
5.5 V
1.65
IOL = 75 mA
5.5 V
1.65
II
VI = VCC or GND
5.5 V
0.1
1
1
A
IOZ
VO = VCC or GND
5.5 V
0.5
10
5
A
ICC
VI = VCC or GND,
IO = 0
5.5 V
8
160
80
A
ICC
One input at 3.4 V,
Other inputs at VCC or GND
5.5 V
0.9
1
1
mA
Ci
VI = VCC or GND
5 V
4.5
pF
Co
VO = VCC or GND
5 V
12
pF
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
timing requirements over recommended operating free-air temperature range, V
CC
= 5 V
0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25
C
54ACT11821
74ACT11821
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
0
125
0
125
0
125
MHz
tw
Pulse duration, CLK high or low
4
4
4
ns
tsu
Setup time, data before CLK
2.5
2.5
2.5
ns
th
Hold time, data after CLK
1.5
1.5
1.5
ns
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25
C
54ACT11821
74ACT11821
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
fmax
125
125
125
MHz
tPLH
CLK
Any Q
4.7
7.6
10.4
4.7
12.6
4.7
11.7
ns
tPHL
CLK
Any Q
5
8.1
11
5
12.9
5
12.1
ns
tPZH
OE
Any Q
3.1
6.1
9.1
3.1
10.8
3.1
10
ns
tPZL
OE
Any Q
4.1
7.6
11
4.1
13.2
4.1
12.3
ns
tPHZ
OE
Any Q
4.8
7.2
9.2
4.8
10.6
4.8
10.1
ns
tPLZ
OE
Any Q
4.8
6.8
8.6
4.8
9.8
4.8
9.4
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
54ACT11821, 74ACT11821
10-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS156A NOVEMBER 1990 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
25
operating characteristics, V
CC
= 5 V, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
C d
Power dissipation capacitance per flip flop
Outputs enabled
CL = 50 pF
f = 1 MHz
45
pF
Cpd
Power dissipation capacitance per flip-flop
Outputs disabled
CL = 50 pF,
f = 1 MHz
31
pF
PARAMETER MEASUREMENT INFORMATION
50% VCC
1.5 V
1.5 V
1.5 V
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
1.5 V
1.5 V
3 V
0 V
50% VCC
50% VCC
Input
(see Note B)
Out-of-Phase
Output
In-Phase
Output
Timing Input
(see Note B)
50% VCC
VOLTAGE WAVEFORMS
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
2
VCC
500
500
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2
VCC
(see Note C)
Output
Waveform 2
S1 at GND
(see Note C)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V
1.5 V
[
VCC
0 V
50% VCC
20% VCC
50% VCC
80% VCC
[
0 V
3 V
GND
Open
VOLTAGE WAVEFORMS
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2
VCC
GND
TEST
S1
3 V
0 V
1.5 V
1.5 V
tw
VOLTAGE WAVEFORMS
Input
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr = 3 ns, tf = 3 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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