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Электронный компонент: 54ACT16646WD

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54ACT16646, 74ACT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS127B MARCH 1990 REVISED APRIL 1996
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Members of the Texas Instruments
Widebus
t
Family
D
Inputs Are TTL-Voltage Compatible
D
Independent Registers for A and B Buses
D
Multiplexed Real-Time and Stored Data
D
Flow-Through Architecture Optimizes
PCB Layout
D
Distributed V
CC
and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
EPIC
t
(Enhanced-Performance Implanted
CMOS) 1-
m
m Process
D
500-mA Typical Latch-Up Immunity at
125
C
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Pin Spacings
description
The 'ACT16646 are 16-bit bus transceivers
consisting of D-type flip-flops and control circuitry
with 3-state outputs arranged for multiplexed
transmission of data directly from the data bus or
from the internal storage registers. The devices
can be used as two 8-bit transceivers or one 16-bit
transceiver. Data on the A or B bus is clocked into
the registers on the low-to-high transition of the
appropriate clock (CLKAB or CLKBA) input.
Figure 1 illustrates the four fundamental bus-
management functions that can be performed
with the bus transceivers and registers.
Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the
transceiver mode, data present at the high-impedance port may be stored in either register or in both. The select
controls (SAB and SBA) can multiplex stored and real-time (transparent mode) data. The circuitry used for
select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between
stored and real-time data. DIR determines which bus receives data when OE is low. In the isolation mode (OE
high), A data may be stored in one register and/or B data may be stored in the other register.
When an output function is disabled, the input function is still enabled and may be used to store and transmit
data. Only one of the two buses, A or B, may be driven at a time.
The 74ACT16646 is packaged in TI's shrink small-outline package, which provides twice the functionality of
standard small-outline packages in the same printed-circuit-board area.
The 54ACT16646 is characterized for operation over the full military temperature range of 55
C to 125
C. The
74ACT16646 is characterized for operation from 40
C to 85
C.
Copyright
1996, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
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22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1DIR
1CLKAB
1SAB
GND
1A1
1A2
V
CC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
CC
2A7
2A8
GND
2SAB
2CLKAB
2DIR
1OE
1CLKBA
1SBA
GND
1B1
1B2
V
CC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V
CC
2B7
2B8
GND
2SBA
2CLKBA
2OE
54ACT16646 . . . WD PACKAGE
74ACT16646 . . . DL PACKAGE
(TOP VIEW)
54ACT16646, 74ACT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS127B MARCH 1990 REVISED APRIL 1996
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
L
DIR
L
CLKAB
X
CLKBA
X
SAB
X
SBA
L
REAL-TIME TRANSFER
BUS B TO BUS A
L
DIR
H
CLKAB
X
CLKBA
X
SAB
L
SBA
X
REAL-TIME TRANSFER
BUS A TO BUS B
X
DIR
X
CLKAB CLKBA
X
SAB
X
SBA
X
STORAGE FROM
A, B, OR A AND B
L
DIR
L
CLKAB
X
CLKBA
H or L
SAB
X
SBA
H
TRANSFER STORED DATA
TO A AND/OR B
X
H
X
X
X
X
X
X
X
L
H
H or L
X
H
X

BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
OE
OE
OE
OE
Figure 1. Bus-Management Functions
54ACT16646, 74ACT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS127B MARCH 1990 REVISED APRIL 1996
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
DATA I/O
OPERATION OR FUNCTION
OE
DIR
CLKAB
CLKBA
SAB
SBA
A1A8
B1B8
OPERATION OR FUNCTION
X
X
X
X
X
Input
Unspecified
Store A, B unspecified
{
X
X
X
X
X
Unspecified
Input
Store B, A unspecified
{
H
X
X
X
Input
Input
Store A and B data
H
X
H or L
H or L
X
X
Input
Input
Isolation, hold storage
L
L
X
X
X
L
Output
Input
Real-time B data to A bus
L
L
X
H or L
X
H
Output
Input
Stored B data to A bus
L
H
X
X
L
X
Input
Output
Real-time A data to B Bus
L
H
H or L
X
H
X
Input
Output
Stored A data to bus
The data-output functions may be enabled or disabled by various signals at OE or DIR. Data-input functions are always enabled, i.e., data at
the bus terminals is stored on every low-to-high transition of the clock inputs.
54ACT16646, 74ACT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS127B MARCH 1990 REVISED APRIL 1996
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic symbol
1A2
6
1A3
8
1A4
9
1A5
10
1A6
12
1A7
13
1A8
14
2A2
16
2A3
17
2A4
19
2A5
20
2A6
21
2A7
23
2A8
24
5
1A1
1B6
45
1B7
44
1B8
43
1B2
51
1B3
49
1B4
48
1B5
47
1B1
52
4D
1
2
G12
31
2SBA
30
2CLKBA
10 EN8 [BA]
28
2DIR
G10
29
2B6
36
2B7
34
2B8
33
2B2
41
2B3
40
2B4
38
2B5
37
2OE
10 EN9 [AB]
1
1
5
5
1
1
7
7
15
2A1
8
9
1
1
12
12
1
1
14
14
13D
2B1
42
11D
C11
G14
26
2SAB
27
2CLKAB
C13
G5
54
1SBA
55
1CLKBA
3 EN1 [BA]
1
1DIR
G3
56
1OE
3 EN2 [AB]
C4
G7
3
1SAB
2
1CLKAB
C6
6D
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
54ACT16646, 74ACT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS127B MARCH 1990 REVISED APRIL 1996
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram (positive logic)
B8
B7
B6
B5
B4
B3
B2
33
34
36
37
38
40
41
2A8
2A7
2A6
2A5
2A4
2A3
2A2
24
23
21
20
19
17
16
2A1
2SAB
2CLKAB
2SBA
2CLKBA
2DIR
2OE
15
26
27
31
30
28
29
TG
TG
TG
TG
C1
1D
1D
C1
42
B1
Seven Channels Identical
to Channel One Above
Seven Channels Identical
to Channel One Above
B8
B7
B6
B5
B4
B3
B2
B1
47
48
49
51
52
1A8
1A7
1A6
1A5
1A4
1A3
1A2
14
13
12
10
9
8
6
1A1
5
1SAB
1CLKAB
1SBA
1CLKBA
1DIR
1OE
3
2
54
55
1
56
C1
1D
1D
C1
TG
TG
TG
TG
45
44
43