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54ACT16825, 74ACT16825
18-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS155B JANUARY 1991 REVISED APRIL 1996
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Members of the Texas Instruments
Widebus
TM
Family
D
Inputs Are TTL-Voltage Compatible
D
Provide Extra Data Width Necessary for
Wider Address/Data Paths or Buses With
Parity
D
Flow-Through Architecture Optimizes
PCB Layout
D
Distributed V
CC
and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
EPIC
TM
(Enhanced-Performance Implanted
CMOS) 1-
m Process
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Spacings
description
The 'ACT16825 18-bit buffers/drivers are
designed specifically to improve both the
performance and density of 3-state memory
address drivers, clock drivers, and bus-oriented
receivers and transmitters.
The 'ACT16825 can be used as two 9-bit buffers
or one 18-bit buffer. They provide true data from
A to Y.
The 3-state control gate is a 2-input NOR gate;
therefore, if either output-enable (OE1 or OE2)
input is high, all nine affected outputs are in the
high-impedance state.
The 74ACT16825 is packaged in TI's shrink small-outline package, which provides twice the I/O pin count and
functionality of standard small-outline packages in the same printed-circuit-board area.
The 54ACT16825 is characterized for operation over the full military temperature range of 55
C to 125
C. The
74ACT16825 is characterized for operation from 40
C to 85
C.
FUNCTION TABLE
(each 9-bit section)
INPUTS
OUTPUT
OE1
OE2
A
Y
L
L
L
L
L
L
H
H
H
X
X
Z
X
H
X
Z
Copyright
1996, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
54ACT16825 . . . DW PACKAGE
74ACT16825 . . . DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OE1
1Y1
1Y2
GND
1Y3
1Y4
V
CC
1Y5
1Y6
1Y7
GND
1Y8
1Y9
GND
GND
2Y1
2Y2
GND
2Y3
2Y4
2Y5
V
CC
2Y6
2Y7
GND
2Y8
2Y9
2OE1
1OE2
1A1
1A2
GND
1A3
1A4
V
CC
1A5
1A6
1A7
GND
1A8
1A9
GND
GND
2A1
2A2
GND
2A3
2A4
2A5
V
CC
2A6
2A7
GND
2A8
2A9
2OE2
54ACT16825, 74ACT16825
18-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS155B JANUARY 1991 REVISED APRIL 1996
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic symbol
55
1A1
1Y1
2
54
1A2
1Y2
3
52
1A3
1Y3
5
51
1A4
1Y4
6
49
1A5
1Y5
8
48
1A6
1Y6
9
47
1A7
1Y7
10
45
1A8
1Y8
12
44
1A9
1Y9
13
1
41
2A1
2Y1
16
40
2A2
2Y2
17
38
2A2
2Y3
19
37
2A3
2Y4
20
36
2A4
2Y5
21
34
2A5
2Y6
23
33
2A6
2Y7
24
31
2A7
2Y8
26
30
2A8
2Y9
27
2
1
56
28
29
1OE1
1OE2
2OE1
2OE2
&
&
EN1
EN2
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1Y1
2
1
55
56
To Eight Other Channels
2Y1
16
28
41
29
To Eight Other Channels
2OE1
2OE2
2A1
1OE1
1OE2
1A1
54ACT16825, 74ACT16825
18-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS155B JANUARY 1991 REVISED APRIL 1996
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
450 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum package power dissipation at T
A
= 55
C (in still air) (see Note 2): DL package
1.4 W
. . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150
_
C and a board trace length of 750 mils.
recommended operating conditions (see Note 3)
54ACT16825
74ACT16825
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
VCC
Supply voltage
4.5
5
5.5
4.5
5
5.5
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
VI
Input voltage
0
VCC
0
VCC
V
VO
Output voltage
0
VCC
0
VCC
V
IOH
High-level output current
24
24
mA
IOL
Low-level output current
24
24
mA
t/
v
Input transition rise or fall rate
0
10
0
10
ns/V
TA
Operating free-air temperature
55
125
40
85
C
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
54ACT16825, 74ACT16825
18-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS155B JANUARY 1991 REVISED APRIL 1996
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
54ACT16825
74ACT16825
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
IOH = 50
A
4.5 V
4.4
4.4
4.4
IOH = 50
A
5.5 V
5.4
5.4
5.4
VOH
IOH = 24 mA
4.5 V
3.94
3.8
3.8
V
IOH = 24 mA
5.5 V
4.94
4.8
4.8
IOH = 75 mA
5.5 V
3.85
3.85
IOL = 50
A
4.5 V
0.1
0.1
0.1
IOL = 50
A
5.5 V
0.1
0.1
0.1
VOL
IOL = 24 mA
4.5 V
0.36
0.44
0.44
V
IOL = 24 mA
5.5 V
0.36
0.44
0.44
IOL = 75 mA
5.5 V
1.65
1.65
II
VI = VCC or GND
5.5 V
0.1
1
1
A
IOZ
VO = VCC or GND
5.5 V
0.5
5
5
A
ICC
VI = VCC or GND,
IO = 0
5.5 V
8
8 0
8 0
A
ICC
One input at 3.4 V,
Other inputs at VCC or GND
5.5 V
0.9
1
1
mA
Ci
VI = VCC or GND
5 V
4
pF
Co
VO = VCC or GND
5 V
16
pF
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25
C
54ACT16825
74ACT16825
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
tPLH
A
Y
4.1
7.5
9.3
4.1
10.5
4.1
10.5
ns
tPHL
A
Y
3.1
7.5
9.6
3.1
10.3
3.1
10.3
ns
tPZH
OE
Y
3.3
7.9
9.9
3.3
11
3.3
11
ns
tPZL
OE
Y
4.1
9.5
12.1
4.1
13.2
4.1
13.2
ns
tPHZ
OE
Y
5.7
9
10.8
5.7
11.5
5.7
11.5
ns
tPLZ
OE
Y
5.5
8.5
10
5.5
10.6
5.5
10.6
ns
operating characteristics, V
CC
= 5 V, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
C d
Power dissipation capacitance
Outputs enabled
CL = 50 pF
f = 1 MHz
42
pF
Cpd
Power dissipation capacitance
Outputs disabled
CL = 50 pF,
f = 1 MHz
12
pF
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
54ACT16825, 74ACT16825
18-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS155B JANUARY 1991 REVISED APRIL 1996
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50% VCC
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
1.5 V
1.5 V
3 V
0 V
50% VCC
50% VCC
Input
Out-of-Phase
Output
In-Phase
Output
50% VCC
VOLTAGE WAVEFORMS
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
2
VCC
500
500
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2
VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V
1.5 V
[
VCC
0 V
50% VCC
20% VCC
50% VCC
80% VCC
[
0 V
3 V
GND
Open
VOLTAGE WAVEFORMS
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2
VCC
GND
TEST
S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
1 MHz, ZO = 50
, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms