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THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B MAY 2000 REVISED DECEMBER 2002
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
features
D
Simultaneous Sampling of 2 Single-Ended
Signals or 1 Differential Signal
D
Integrated 16 Word FIFO
D
Signal-to-Noise and Distortion Ratio: 66 dB
at f
I
= 2 MHz
D
Differential Nonlinearity Error:
1 LSB
D
Integral Nonlinearity Error:
1.5 LSB
D
Auto-Scan Mode for 2 Inputs
D
3-V or 5-V Digital Interface Compatible
D
Low Power: 216 mW Max
D
5-V Analog Single Supply Operation
D
Internal Voltage References . . . 50 PPM/
C
and
5% Accuracy
D
Parallel
C/DSP Interface
applications
D
Radar Applications
D
Communications
D
Control Applications
D
High-Speed DSP Front-End
D
Automotive Applications
description
The THS12082 is a CMOS, low-power, 12-bit, 8 MSPS analog-to-digital converter (ADC). The speed,
resolution, bandwidth, and single-supply operation are suited for applications in radar, imaging, high-speed
acquisition, and communications. A multistage pipelined architecture with output error correction logic provides
for no missing codes over the full operating temperature range. Internal control registers allow for programming
the ADC into the desired mode. The THS12082 consists of two analog inputs, which are sampled
simultaneously. These inputs can be selected individually and configured to single-ended or differential inputs.
An integrated 16 word deep FIFO allows the storage of data in order to take the load off of the processor
connected to the ADC. Internal reference voltages for the ADC (1.5 V and 3.5 V) are provided.
An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the
application. Two different conversion modes can be selected. In the single conversion mode, a single and
simultaneous conversion can be initiated by using the single conversion start signal (CONVST). The conversion
clock in the single conversion mode is generated internally using a clock oscillator circuit. In the continuous
conversion mode, an external clock signal is applied to the CONV_CLK input of the THS12082. The internal
clock oscillator is switched off in the continuous conversion mode.
The THS12082C is characterized for operation from 0
C to 70
C, and the THS12082I is characterized for
operation from 40
C to 85
C.
Copyright
2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
D0
D1
D2
D3
D4
D5
BV
DD
BGND
D6
D7
D8
D9
RA0/D10
RA1/D11
CONV_CLK (CONVST)
DATA_AV
OV_FL
RESET
AINP
AINM
REFIN
REFOUT
REFP
REFM
AGND
AV
DD
CS0
CS1
WR (R/W)
RD
DV
DD
DGND
DA PACKAGE
(TOP VIEW)
THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B MAY 2000 REVISED DECEMBER 2002
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
AVAILABLE OPTIONS
PACKAGED DEVICE
TA
TSSOP
(DA)
0
C to 70
C
THS12082CDA
40
C to 85
C
THS12082IDA
functional block diagram
Logic
and
Control
Control
Register
S/H
S/H
Single-Ended
and/or
Differential
MUX
12-Bit
Pipeline
ADC
+
REFP
REFM
1.225 V
REF
2.5 V
FIFO
16
12
12
12
Buffers
REFOUT
DATA_AV
OV_FL
BVDD
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10/RA0
D11/RA1
BGND
AGND
DGND
3.5 V
1.5 V
AVDD
DVDD
REFP
REFM
AINP
AINM
CONV_CLK (CONVST)
CS0
CS1
RD
WR (R/W)
RESET
REFIN
THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B MAY 2000 REVISED DECEMBER 2002
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
AINP
30
I
Analog input, single-ended or positive input of differential channel A
AINM
29
I
Analog input, single-ended or negative input of differential channel A
AVDD
23
I
Analog supply voltage
AGND
24
I
Analog ground
BVDD
7
I
Digital supply voltage for buffer
BGND
8
I
Digital ground for buffer
CONV_CLK
(CONVST)
15
I
Digital input. This input is used to apply an external conversion clock in the continuous conversion mode.
In the single conversion mode, this input functions as the conversion start (CONVST) input. A high to low
transition on this input holds simultaneously the selected analog input channels and initiates a single
conversion of all selected analog inputs.
CS0
22
I
Chip select input (active low)
CS1
21
I
Chip select input (active high)
DATA_AV
16
O
Data available signal, which can be used to generate an interrupt for processors and as a level
information of the internal FIFO. This signal can be configured to be active low or high and can be
configured as a static level or pulse output. See Table 14.
DGND
17
I
Digital ground. Ground reference for digital circuitry.
DVDD
18
I
Digital supply voltage
D0 D9
16, 912
I/O/Z
Digital input, output; D0 = LSB
RA0/D10
13
I/O/Z
Digital input, output. The data line D10 is also used as an address line (RA0) for the control register. This
is required for writing to control register 0 and control register 1. See Table 8.
RA1/D11
14
I/O/Z
Digital input, output (D11 = MSB). The data line D11 is also used as an address line (RA1) for the control
register. This is required for writing to control register 0 and control register 1. See Table 8.
OV_FL
32
O
Overflow output. Indicates whether an overflow in the FIFO occurred. OV_FL is set to active high level if
an overflow occurs. It is set back to low level with a reset of the THS12082 or a reset of the FIFO.
REFIN
28
I
Common-mode reference input for the analog input channels. It is recommended that this pin be
connected to the reference output REFOUT.
REFP
26
I
Reference input, requires a bypass capacitor of 10
F to AGND in order to bypass the internal reference
voltage. An external reference voltage at this input can be applied. This option can be programmed
through control register 0. See Table 9.
REFM
25
I
Reference input, requires a bypass capacitor of 10
F to AGND in order to bypass the internal reference
voltage. An external reference voltage at this input can be applied. This option can be programmed
through control register 0. See Table 9.
RESET
31
I
Hardware reset of the THS12082. Sets the control register to default values.
REFOUT
27
O
Analog fixed reference output voltage of 2.5 V. Sink and source capability of 250
A. The reference
output requires a capacitor of 10
F to AGND for filtering and stability.
RD
19
I
The RD input is used only if the WR input is configured as a write only input. In this case, it is a digital input,
active low as a data read select from the processor. See timing section.
WR (R/W)
20
I
This input is programmable. It functions as a read-write input (R/W) and can also be configured as a
write-only input (WR), which is active low and used as data write select from the processor. In this case,
the RD input is used as a read input from the processor. See timing section.
The start-conditions of RD and WR (R/W) are unknown. The first access to the ADC has to be a write access to initialize the ADC.
THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B MAY 2000 REVISED DECEMBER 2002
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range: DGND to DV
DD
0.3 V to 6.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BGND to BV
DD
0.3 V to 6.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AGND to AV
DD
0.3 V to 6.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog input voltage range
AGND 0.3 V to AV
DD
+ 1.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference input voltage
0.3 + AGND to AV
DD
+ 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital input voltage range
0.3 V to BV
DD
/DV
DD
+ 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating
virtual junction temperature range, T
J
40
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range: THS12082C
0
C to 70
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
THS12082I
40
C to 85
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
power supply
MIN
NOM
MAX
UNIT
AVDD
4.75
5
5.25
Supply voltage
DVDD
3
3.3
5.25
V
BVDD
3
3.3
5.25
analog and reference inputs
MIN
NOM
MAX
UNIT
Analog input voltage in single-ended configuration
VREFM
VREFP
V
Common-mode input voltage VCM in differential configuration
1
2.5
4
V
External reference voltage,VREFP (optional)
3.5
AVDD1.2
V
External reference voltage, VREFM (optional)
1.4
1.5
V
Input voltage difference, REFP REFM
2
V
digital inputs
MIN
NOM
MAX
UNIT
High level input voltage VIH
BVDD = 3 V
2
V
High-level input voltage, VIH
BVDD = 5.25 V
2.6
V
Low level input voltage VIL
BVDD = 3 V
0.6
V
Low-level input voltage, VIL
BVDD = 5.25 V
0.6
V
Input CONV_CLK frequency
DVDD = 3 V to 5.25 V
0.1
8
MHz
CONV_CLK pulse duration, clock high, tw(CONV_CLKH)
DVDD = 3 V to 5.25 V
62
83
5000
ns
CONV_CLK pulse duration, clock low, tw(CONV_CLKL)
DVDD = 3 V to 5.25 V
62
83
5000
ns
Operating free air temperature TA
THS12082CDA
0
70
C
Operating free-air temperature, TA
THS12082IDA
40
85
C
THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B MAY 2000 REVISED DECEMBER 2002
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions, V
REFP
= 3.5 V, V
REFM
= 1.5 V
(unless otherwise noted)
digital specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital inputs
IIH
High-level input current
DVDD = digital inputs
50
50
A
IIL
Low-level input current
Digital input = 0 V
50
50
A
Ci
Input capacitance
5
pF
Digital outputs
VOH
High-level output voltage
IOH = 50
A,
BVDD = 3.3 V, 5 V
BVDD0.5
V
VOL
Low-level output voltage
IOL = 50
A,
BVDD = 3.3 V, 5 V
0.4
V
IOZ
High-impedance-state output current
CS1 = DGND,
CS0 = DVDD
10
10
A
CO
Output capacitance
5
pF
CL
Load capacitance at databus D0D11
30
pF
electrical characteristics over recommended operating conditions, AV
DD
= 5 V,
DV
DD
= BV
DD
= 3.3-V, f
s
= 8 MSPS, V
REF
= internal (unless otherwise noted)
dc specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Resolution
12
Bits
Accuracy
Integral nonlinearity, INL
1.5
LSB
Differential nonlinearity, DNL
1
LSB
Offset error
After calibration in single-ended mode
20
LSB
Offset error
After calibration in differential mode
20
20
LSB
Gain error
20
20
LSB
Analog input
Input capacitance
15
pF
Input leakage current
VAIN = VREFM to VREFP
10
A
Internal voltage reference
Accuracy, VREFP
3.3
3.5
3.7
V
Accuracy, VREFM
1.4
1.5
1.6
V
Temperature coefficient
50
PPM/
C
Reference noise
100
V
Accuracy, REFOUT
2.475
2.5
2.525
V
Power supply
IDDA
Analog supply current
AVDD =5 V,
BVDD = DVDD = 3.3 V
36
40
mA
IDDD
Digital supply current
AVDD = 5 V
BVDD = DVDD = 3.3 V
0.5
1
mA
IDDB
Buffer supply current
AVDD = 5 V,
BVDD = DVDD = 3.3 V
1.5
4
mA
IDD_AP
Analog supply current in power-down mode
AVDD = 5 V,
BVDD = DVDD = 3.3 V
8
mA
Power dissipation
AVDD = 5 V,
DVDD = BVDD = 3.3 V
186
216
mW
Power dissipation in power down
AVDD = 5 V,
DVDD = BVDD = 3.3 V
30
mW