Document Outline

• features
• description
• JTAG scan-based emulation logic
• pinout
  • GNM Terminal Assignments (Sorted by Signal Name)
  • GNM Terminal Assignments (Sorted by Pin Number)
• Terminal Functions
• functional block diagram
• memory map
  • clock generator
  • PLL and clock oscillator control
  • PLL isolation
• clock and PLL considerations on initialization
• power sequencing considerations
  • EDGEMODE
  • reset operation
  • PAGE0\ - PAGE3\ select lines
• using external logic with the READY\ pin
  • example 1
  • example 2
• posted writes
  • data bus I/O buffer
  • bootloader operation
• JTAG emulation
• designing a target system emulator connector (14-pin header)
• JTAG emulator cable pod logic
• device and development support tool nomenclature
  • SMX
  • TMP
  • SM/SMJ
  • TMDX
  • TMDS
• absolute maximum ratings over specified temperature range (unless other\ wise noted)
• recommended operating conditions
• electrical characteristics over recommended ranges of supply voltage (u\ nless otherwise noted)
• PARAMETER MEASUREMENT INFORMATION
• PARAMETER MEASUREMENT INFORMATION
  • timing parameter symbology
• phase-locked loop (PLL) circuit timing
  • phase-locked loop characteristics using EXTCLK or on-chip crystal oscill\ ator
• clock circuit timing
  • circuit parameters for on-chip crystal oscillator � (see Figure 15)
  • timing requirements for EXTCLK, all modes (see Figure 16 and Figure 17)\
  • switching characteristics for EXTCLK over recommended operating conditio\ ns, all modes (see Figure 16 and Figure 17)
• memory read/write timing
  • timing requirements for memory read/write � (see Figure 18, Figure 19, \ and Figure 20)
  • switching characteristics over recommended operating conditions for memo\ ry read/write (see Figure 18, Figure 19, and Figure 20)
• XF0 and XF1 timing when executing LDFI or LDII
  • timing requirements for XF0 and XF1 when executing LDFI or LDII (see Fi\ gure 21)
  • switching characteristics over recommended operating conditions for XF0 \ and XF1 when executing LDFI or LDII (see Figure 21)
• XF0 timing when executing STFI and STII
  • switching characteristics over recommended operating conditions for XF0 \ when executing STFI or STII (see Figure 22)
• XF0 and XF1 timing when executing SIGI
  • timing requirements for XF0 and XF1 when executing SIGI (see Figure 23)\
  • switching characteristics over recommended operating conditions for XF0 \ and XF1 when executing SIGI (see Figure 23)
• loading when XF is configured as an output
  • switching characteristics over recommended operating conditions for load\ ing the XF register when configured as an output pin (see Figure 24)
• changing XFx from an output to an input
  • timing requirements for changing XFx from output to input mode (see Fig\ ure 25)
  • switching characteristics over recommended operating conditions for chan\ ging XFx from output to input mode (see Figure 25)
• changing XFx from an input to an output
  • switching characteristics over recommended operating conditions for chan\ ging XFx from input to output mode (see Figure 26)
• reset timing
  • timing requirements for RESET\ (see Figure 27)
  • switching characteristics over recommended operating conditions for RESE\ T (see Figure 27)
• interrupt response timing
  • timing requirements for INT3\-INT0\ response (see Figure 28)
• interrupt-acknowledge timing
  • switching characteristics over recommended operating conditions for IACK\ \ (see Figure 29)
• serial-port timing parameters
  • timing requirements (see Figure 30 and Figure 31)
  • switching characteristics over recommended operating conditions (see Fi\ gure 30 and Figure 31)
• data-rate timing modes
• HOLD\ timing
  • timing requirements for HOLD\/HOLDA\ (see Figure 32 and Figure 33)
  • switching characteristics over recommended operating conditions for HOLD\ \/HOLDA\ (see Figure 32 and Figure 33)
• general-purpose I/O timing
  • peripheral pin I/O timing
    • timing requirements for peripheral pin general-purpose I/O (see Note 1,\ Figure 34, and Figure 35)
    • switching characteristics over recommended operating conditions for peri\ pheral pin general- purpose I/ O (see Note 1, Figure 34, and Figure 35)\
• timer pin timing
  • timing requirements for timer pin (see Figure 36 and Figure 37)
  • switching characteristics over recommended operating conditions for time\ r pin (see Figure 36 and Figure 37)
• SHZ\ pin timing
  • switching characteristics over recommended operating conditions for SHZ\\ (see Figure 38)
• test access port timing
  • timing for test access port (see Figure 39)
• MECHANICAL DATA
  • GNM (S-CBGA-N144) CERAMIC BALL GRID ARRAY
  • HFG (S-CQFP-F164) CERAMIC QUAD FLATPACK WITH NCTB