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SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B OCTOBER 1975 REVISED AUGUST 2002
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Choice of Eight Latches or Eight D-Type
Flip-Flops in a Single Package
D
3-State Bus-Driving Outputs
D
Full Parallel Access for Loading
D
Buffered Control Inputs
D
Clock-Enable Input Has Hysteresis to
Improve Noise Rejection ('S373 and 'S374)
D
P-N-P Inputs Reduce DC Loading on Data
Lines ('S373 and 'S374)
description
These 8-bit registers feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. The
high-impedance 3-state and increased
high-logic-level drive provide these registers with
the capability of being connected directly to and
driving the bus lines in a bus-organized system
without need for interface or pullup components.
These devices are particularly attractive for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
The eight latches of the 'LS373 and 'S373 are
transparent D-type latches, meaning that while
the enable (C or CLK) input is high, the Q outputs
follow the data (D) inputs. When C or CLK is taken
low, the output is latched at the level of the data
that was set up.
The eight flip-flops of the 'LS374 and 'S374 are
edge-triggered D-type flip-flops. On the positive
transition of the clock, the Q outputs are set to the
logic states that were set up at the D inputs.
Schmitt-trigger buffered inputs at the enable/clock lines of the 'S373 and 'S374 devices simplify system design
as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered
output-control (OC) input can be used to place the eight outputs in either a normal logic state (high or low logic
levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly.
OC does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new
data can be entered, even while the outputs are off.
Copyright
2002, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54LS373, SN54LS374, SN54S373,
SN54S374 . . . J OR W PACKAGE
SN74LS373, SN74S374 . . . DW, N, OR NS PACKAGE
SN74LS374 . . . DB, DW, N, OR NS PACKAGE
SN74S373 . . . DW OR N PACKAGE
(TOP VIEW)
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
8D
7D
7Q
6Q
6D
2D
2Q
3Q
3D
4D
SN54LS373, SN54LS374, SN54S373,
SN54S374 . . . FK PACKAGE
(TOP VIEW)
1D
1Q
OC
5Q
5D
8Q
4Q
GND
C
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OC
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
C
C for 'LS373 and 'S373; CLK for 'LS374 and 'S374.
C for 'LS373 and 'S373; CLK for 'LS374 and 'S374.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B OCTOBER 1975 REVISED AUGUST 2002
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
Tube
SN74LS373N
SN74LS373N
PDIP
N
Tube
SN74LS374N
SN74LS374N
PDIP N
Tube
SN74S373N
SN74S373N
Tube
SN74S374N
SN74S374N
Tube
SN74LS373DW
LS373
Tape and reel
SN74LS373DWR
LS373
Tube
SN74LS374DW
LS374
0
C to 70
C
SOIC
DW
Tape and reel
SN74LS374DWR
LS374
0
C to 70
C
SOIC DW
Tube
SN74S373DW
S373
Tape and reel
SN74S373DWR
S373
Tube
SN74S374DW
S374
Tape and reel
SN74S374DWR
S374
Tape and reel
SN74LS373NSR
74LS373
SOP NS
Tape and reel
SN74LS374NSR
74LS374
Tape and reel
SN74S374NSR
74S374
SSOP DB
Tape and reel
SN74LS374DBR
LS374A
Tube
SN54LS373J
SN54LS373J
Tube
SNJ54LS373J
SNJ54LS373J
Tube
SN54LS374J
SN54LS374J
CDIP
J
Tube
SNJ54LS374J
SNJ54LS374J
CDIP J
Tube
SN54S373J
SN54S373J
Tube
SNJ54S373J
SNJ54S373J
Tube
SN54S374J
SN54S374J
55
C to 125
C
Tube
SNJ54S374J
SNJ54S374J
Tube
SNJ54LS373W
SNJ54LS373W
CFP W
Tube
SNJ54LS374W
SNJ54LS374W
Tube
SNJ54S374W
SNJ54S374W
Tube
SNJ54LS373FK
SNJ54LS373FK
LCCC
FK
Tube
SNJ54LS374FK
SNJ54LS374FK
LCCC FK
Tube
SNJ54S373FK
SNJ54S373FK
Tube
SNJ54S374FK
SNJ54S374FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B OCTOBER 1975 REVISED AUGUST 2002
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Function Tables
'LS373, 'S373
(each latch)
INPUTS
OUTPUT
OC
C
D
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
'LS374, 'S374
(each latch)
INPUTS
OUTPUT
OC
CLK
D
Q
L
H
H
L
L
L
L
L
X
Q0
H
X
X
Z
SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B OCTOBER 1975 REVISED AUGUST 2002
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagrams (positive logic)
OC
for 'S373 Only
1
11
3
2
C
1D
C1
1D
1Q
4
5
2D
C1
1D
2Q
7
6
3D
C1
1D
3Q
8
9
4D
C1
1D
4Q
13
12
5D
C1
1D
5Q
14
15
6D
C1
1D
6Q
17
16
7D
C1
1D
7Q
18
19
8D
C1
1D
8Q
Pin numbers shown are for DB, DW, J, N, NS, and W packages.
OC
for 'S374 Only
1
11
3
2
CLK
1D
C1
1D
1Q
4
5
2D
1D
2Q
7
6
3D
1D
3Q
8
9
4D
1D
4Q
13
12
5D
1D
5Q
14
15
6D
1D
6Q
17
16
7D
1D
7Q
18
19
8D
1D
8Q
'LS373, 'S373
Transparent Latches
'LS374, 'S374
Positive-Edge-Triggered Flip-Flops
C1
C1
C1
C1
C1
C1
C1
SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B OCTOBER 1975 REVISED AUGUST 2002
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
schematic of inputs and outputs
Output
TYPICAL OF ALL OUTPUTS
VCC
100
NOM
VCC
Req = 20 k
NOM
Input
Input
VCC
17 k
NOM
'LS373
EQUIVALENT OF DATA INPUTS
EQUIVALENT OF ENABLE- AND
OUTPUT-CONTROL INPUTS
EQUIVALENT OF CLOCK- AND
OUTPUT-CONTROL INPUTS
'LS374
EQUIVALENT OF DATA INPUTS
30 k
NOM
Input
VCC
17 k
NOM
VCC
Input
Output
TYPICAL OF ALL OUTPUTS
VCC
100
NOM