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TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M
HIGH-PERFORMANCE IMPACT
TM
PAL
CIRCUITS
SRPS018A D3338, JANUARY 1986 REVISED MAY 1996
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
High-Performance Operation:
Propagation Delay . . . 15 ns Max
D
Power-Up Clear on Registered Devices (All
Register Outputs are Set High, but Voltage
Levels at the Output Pins Go Low)
D
Package Options Include Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Ceramic (J) 300-mil DIPs
D
Dependable Texas Instruments Quality and
Reliability
DEVICE
I
INPUTS
3-STATE
O OUTPUTS
REGISTERED
Q OUTPUTS
I/O
PORTS
PAL16L8
10
2
0
6
PAL16R4
8
0
4 (3-state buffers)
4
PAL16R6
8
0
6 (3-state buffers)
2
PAL16R8
8
0
8 (3-state buffers)
0
description
These programmable array logic devices feature
high speed and functional equivalency when
compared with currently available devices. These
IMPACT-X
TM
circuits combine the latest Advanced
Low-Power Schottky technology with proven
titanium-tungsten fuses to provide reliable,
high-performance substitutes for conventional
TTL logic. Their easy programmability allows for
quick design of custom functions and typically
results in a more compact circuit board. In
addition, chip carriers are available for futher
reduction in board space.
The TIBPAL16' M series is characterized for
operation over the full military temperature range
of 55
C to 125
C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
IMPACT is a trademark of Texas Instruments Incorporated.
PAL is a registered trademark of Advanced Micro Devices Inc.
Pin assignments in operating mode
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
I
I
I
I
I
I
I
I
I
GND
VCC
O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
TIBPAL16L8'
J OR W PACKAGE
(TOP VIEW)
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
TIBPAL16L8'
FK PACKAGE
(TOP VIEW)
I
I
I
O
I/O
O
I
GND
I
V
CC
TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M
HIGH-PERFORMANCE IMPACT
TM
PAL
CIRCUITS
SRPS018A D3338, JANUARY 1986 REVISED MAY 1996
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Pin assignments in operating mode
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CLK
I
I
I
I
I
I
I
I
GND
VCC
I/O
I/O
Q
Q
Q
Q
I/O
I/O
OE
(TOP VIEW)
TIBPAL16R4'
J OR W PACKAGE
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CLK
I
I
I
I
I
I
I
I
GND
VCC
I/O
Q
Q
Q
Q
Q
Q
I/O
OE
(TOP VIEW)
TIBPAL16R6'
J OR W PACKAGE
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CLK
I
I
I
I
I
I
I
I
GND
VCC
Q
Q
Q
Q
Q
Q
Q
Q
OE
(TOP VIEW)
TIBPAL16R8'
J OR W PACKAGE
I
I
CLK
I/O
I/O
I/O
I
GND
V
CC
OE
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
I/O
Q
Q
Q
Q
I
I
I
I
I
(TOP VIEW)
TIBPAL16R4'
FK PACKAGE
I
I
CLK
I/O
Q
I/O
I
GND
V
CC
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
Q
Q
Q
Q
Q
I
I
I
I
I
(TOP VIEW)
OE
TIBPAL16R6'
FK PACKAGE
I
I
CLK
Q
Q
Q
I
GND
V
CC
OE
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
Q
Q
Q
Q
Q
I
I
I
I
I
(TOP VIEW)
TIBPAL16R8'
FK PACKAGE
TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M
HIGH-PERFORMANCE IMPACT
TM
PAL
CIRCUITS
SRPS018A D3338, JANUARY 1986 REVISED MAY 1996
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
functional block diagrams (positive logic)
TIBPAL16L8'
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I
EN
1
&
32 X 64
10
16
16
6
7
7
7
7
7
7
7
7
6
16 x
denotes fused inputs
TIBPAL16R4'
Q
I/O
I/O
I/O
I/O
I
EN
8
16
16
4
7
7
7
8
8
8
7
4
16 x
1
&
32 X 64
1
8
Q
Q
Q
4
1D
I = 1 2
CLK
C1
EN 2
OE
4
TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M
HIGH-PERFORMANCE IMPACT
TM
PAL
CIRCUITS
SRPS018A D3338, JANUARY 1986 REVISED MAY 1996
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
functional block diagrams (positive logic)
TIBPAL16R6'
Q
I/O
I/O
I
EN
8
16
16
2
7
8
8
8
7
2
16 x
1
&
32 X 64
1
8
Q
Q
Q
6
1D
I = 1 2
CLK
C1
EN 2
OE
6
8
Q
8
Q
denotes fused inputs
TIBPAL16R8'
Q
I
8
16
16
8
8
8
8
8
16 x
8
Q
Q
Q
1D
I = 1 2
CLK
C1
EN 2
8
Q
8
Q
&
32 X 64
1
OE
8
Q
8
Q
TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M
HIGH-PERFORMANCE IMPACT
TM
PAL
CIRCUITS
SRPS018A D3338, JANUARY 1986 REVISED MAY 1996
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
TIBPAL16L8-15M logic diagram (positive logic)
0
4
8
12
16
20
24
28
31
I
2
I
3
I
4
I
5
I
6
I
7
I
8
I
9
O
19
I/O
18
I/O
17
I/O
16
I/O
15
I/O
14
I/O
13
O
12
I
11
Increment
I
1
Fuse number = First fuse number + Increment
0
32
64
96
128
160
192
224
256
288
320
352
384
416
448
480
512
544
576
608
640
672
704
736
768
800
832
864
896
928
960
992
1024
1056
1088
1120
1152
1184
1216
1248
1280
1312
1344
1376
1408
1440
1472
1504
1536
1568
1600
1632
1664
1696
1728
1760
1792
1824
1856
1888
1920
1952
1984
2016
First
Fuse
Numbers