AD7524M
Advanced LinCMOS
TM
8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTER
SGLS028A SEPTEMBER 1989 REVISED MARCH 1995
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Advanced LinCMOS
TM
Silicon-Gate
Technology
D
Easily interfaced to Microprocessors
D
On-Chip Data Latches
D
Monotonicity Over Entire A/D Conversion
Range
D
Segmented High-Order Bits Ensure
Low-Glitch Output
D
Designed to Be interchangeable With
Analog Devices AD7524, PMI PM-7524, and
Micro Power Systems MP7524
D
Fast Control Signaling for Digital Signal
Processor Applications Including Interface
With SMJ320
KEY PERFORMANCE SPECIFICATIONS
Resolution
8 Bits
Linearity error
1/2 LSB Max
Power dissipation at VDD = 5 V
5 mW Max
Settling time
100 ns Max
Propagation delay
80 ns Max
description
The AD7524M is an Advanced LinCMOS
TM
8-bit
digital-to-analog converter (DAC) designed for
easy interface to most popular microprocessors.
The AD7524M is an 8-bit multiplying DAC with input latches and with a load cycle similar to the write cycle of
a random access memory. Segmenting the high-order bits minimizes glitches during changes in the
most-significant bits, which produce the highest glitch impulse. The AD7524M provides accuracy to 1/2 LSB
without the need for thin-film resistors or laser trimming, while dissipating less than 5 mW typically.
Featuring operation from a 5-V to 15-V single supply, the AD7524M interfaces easily to most microprocessor
buses or output ports. Excellent multiplying (2 or 4 quadrant) makes the AD7524M an ideal choice for many
microprocessor-controlled gain-setting and signal-control applications.
The AD7524M is characterized for operation from 55
C to 125
C.
AVAILABLE OPTIONS
PACKAGE
TA
CERAMIC CHIP
CARRIER
(FK)
CERAMIC DIP
(J)
55
C to 125
C
AD7524MFK
AD7524MJ
Advanced LinCMOS is a trademark of Texas Instruments Incorporated.
Copyright
1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
OUT1
OUT2
GND
DB7
DB6
DB5
DB4
DB3
R
FB
REF
V
DD
WR
CS
DB0
DB1
DB2
J PACKAGE
(TOP VIEW)
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
V
DD
WR
NC
CS
DB0
GND
DB7
NC
DB6
DB5
FK PACKAGE
(TOP VIEW)
OUT2
OUT1
NC
DB2
DB1
R
REF
DB4
DB3
NC
NCNo internal connection
FB
AD7524M
Advanced LinCMOS
TM
8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTER
SGLS028A SEPTEMBER 1989 REVISED MARCH 1995
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
functional block diagram
Data Inputs
Data Latches
13
WR
12
CS
REF
15
11
6
5
4
DB7
(MSB)
RFB
16
R
R
R
S-8
S-3
S-2
S-1
2R
DB6
DB5
DB0
(LSB)
2R
2R
2R
2R
R
OUT1
OUT2
GND
1
2
3
operating sequence
DB0 DB7
WR
CS
tw(WR)
tsu(CS)
tsu(D)
th(CS)
th(D)
10%
10%
10%
AD7524M
Advanced LinCMOS
TM
8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTER
SGLS028A SEPTEMBER 1989 REVISED MARCH 1995
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
DD
0.3 V to 17 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage between R
FB
and GND
25 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital input voltage range, V
I
0.3 V to V
DD
+0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference voltage range, V
ref
25 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak digital input current, I
I
10
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
55
C to 125
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Case temperature for 60 seconds, T
C
: FK package
260
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package
300
C
. . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
VDD = 5 V
VDD = 15 V
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
Supply voltage, VDD
4.75
5
5.25
14.5
15
15.5
V
Reference voltage, Vref
10
10
V
High-level input voltage, VIH
2.4
13.5
V
Low-level input volage, VIL
0.8
1.5
V
CS setup time, tsu(CS)
40
40
ns
CS hold time, th(CS)
0
0
ns
Data bus input setup time, tsu(D)
25
25
ns
Data bus input hold time, th(D)
10
10
ns
Pulse duration, WR low, tw(WR)
40
40
ns
Operating free-air temperature, TA
55
125
55
125
C
AD7524M
Advanced LinCMOS
TM
8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTER
SGLS028A SEPTEMBER 1989 REVISED MARCH 1995
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range, V
ref
= 10 V,
OUT1 and OUT2 at GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VDD = 5 V
VDD = 15 V
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
IIH
High level input current
VI = VDD
Full-range
10
10
A
IIH
High-level input current
VI = VDD
25
C
1
1
A
IIL
Low level input current
VI = 0
Full-range
10
10
A
IIL
Low-level input current
VI = 0
25
C
1
1
A
OUT1
DB0DB7 at 0,
WR and CS at 0 V
Full-range
400
200
I k
Output leakage
Vref =
10 V
25
C
50
50
nA
Ipkg
g
current
OUT2
DB0DB7 at VDD,
WR and CS at 0
Full-range
400
200
nA
Vref =
10 V
25
C
50
50
Quiescent
DB0DB7 at VIHmin or VILmax
2
2
mA
IDD
Supply current
Standby
DB0 DB7 at 0 V or VDD
Full-range
500
500
A
Standby
DB0DB7 at 0 V or VDD
25
C
100
100
A
kSVS
Supply voltage sensitivity,
VDD = 10%
Full-range
0.16
0.04
%/%
kSVS
y
g
y,
gain/
VDD
VDD = 10%
25
C
0.002
0.02
0.001
0.02
pF
Ci
Input capacitance, DB0DB7,
WR, CS
VI = 0
5
5
pF
OUT1
DB0 DB7 at 0 WR and CS at 0 V
30
30
C
Output
OUT2
DB0DB7 at 0, WR and CS at 0 V
120
120
pF
Co
capacitance
OUT1
DB0 DB7 at V
WR and CS at 0 V
120
120
pF
OUT2
DB0DB7 at VDD, WR and CS at 0 V
30
30
Reference input impedance
(REF to GND)
5
20
5
20
k
operating characteristics over recommended operating free-air temperature range, V
ref
= 10 V,
OUT1 and OUT2 at GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC = 5 V
VDD = 15 V
UNIT
PARAMETER
TEST CONDITIONS
MIN
MAX
MIN
MAX
UNIT
Linearity error
0.2
0.2
%FSR
Gain error
See Note 1
Full range
1.4
0.6
%FSR
Gain error
See Note 1
25
C
1
0.5
%FSR
Settling time (to 1/2 LSB)
See Note 2
100
100
ns
Propagation delay from digital input to
90% of final analog output current
See Note 2
80
80
ns
Feedthrough at OUT1 or OUT2
Vref =
10 V (100 kHz sinewave),
Full range
0.5
0.5
%FSR
Feedthrough at OUT1 or OUT2
ref
(
),
WR and CS at 0, DB0DB7 at 0
25
C
0.25
0.25
%FSR
Temperature coefficient of gain
TA = 25
C to tmin or tmax
0.004
0.001
%FSR/
C
NOTES:
1. Gain error is measured using the internal feedback resistor. Nominal Full Scale Range (FSR) = Vref 1 LSB.
2. OUT1 load = 100
, Cext = 13 pF, WR at 0 V, CS at 0 V, DB0DB7 at 0 V to VDD or VDD to 0 V.
AD7524M
Advanced LinCMOS
TM
8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTER
SGLS028A SEPTEMBER 1989 REVISED MARCH 1995
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
The AD7524M is an 8-bit multiplying D/A converter consisting of an inverted R-2R ladder, analog switches, and
data input latches. Binary weighted currents are switched between the OUT1 and OUT2 bus lines, thus
maintaining a constant current in each ladder leg independent of the switch state. The high-order bits are
decoded and these decoded bits, through a modification in the R-2R ladder, control three equally weighted
current sources. Most applications only require the addition of an external operational amplifier and a voltage
reference.
The equivalent circuit for all digital inputs low is seen in Figure 1. With all digital inputs low, the entire reference
current, I
ref
, is switched to OUT2. The current source 1/256 represents the constant current flowing through the
termination resistor of the R-2R ladder, while the current source I
Ikg
represents leakage currents to the
substrate. The capacitances appearing at OUT1 and OUT2 are dependent upon the digital input code. With all
digital inputs high, the off-state switch capacitance (30 pF maximum) appears at OUT2 and the on-state switch
capacitance (120 pF maximum) appears at OUT1. With all digital inputs low, the situation is reversed as shown
in Figure 1. Analysis of the circuit for all digital inputs high is similar to Figure 1; however, in this case, I
ref
would
be switched to OUT1.
Interfacing the AD7524M D/A converter to a microprocessor is accomplished via the data bus and the CS and
WR control signals. When CS and WR are both low, the AD7524M analog output responds to the data activity
on the DB0DB7 data bus inputs. In this mode, the input latches are transparent and input data directly affects
the analog output. When either the CS signal or WR signal goes high, the data on the DB0DB7 inputs are
latched until the CS and WR signals go low again. When CS is high, the data inputs are disabled regardless
of the state of the WR signal.
The AD7524M is capable of performing 2-quadrant or full 4-quadrant multiplication. Circuit configurations for
2-quadrant or 4-quadrant multiplication are shown in Figures 2 and 3. Input coding for unipolar and bipolar
operation are summarized in Tables 1 and 2, respectively.
PDF 
ZIP