SN54ALS564B, SN74ALS564B
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS164B APRIL 1982 REVISED JANUARY 1995
Copyright
1995, Texas Instruments Incorporated
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
3-State Buffer-Type Inverting Outputs Drive
Bus Lines Directly
Bus-Structured Pinout
Buffered Control Inputs
Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), Standard Plastic (N) and
Ceramic (J) 300-mil DIPs, and Ceramic Flat
(W) Packages
description
These octal D-type edge-triggered flip-flops
feature inverting 3-state outputs designed
specifically for bus driving. They are particularly
suitable for implementing buffer registers, I/O
ports, bidirectional bus drivers, and working
registers.
The eight flip-flops enter data on the low-to-high
transition of the clock (CLK) input.
The output-enable (OE) input does not affect
internal operations of the flip-flops. Old data can
be retained or new data can be entered while the
outputs are in the high-impedance state.
The SN54ALS564B is characterized for operation
over the full military temperature range of 55
C
to 125
C. The SN74ALS564B is characterized for
operation from 0
C to 70
C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
OE
CLK
D
Q
L
H
L
L
L
H
L
L
X
Q0
H
X
X
Z
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
V
CC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
CLK
SN54ALS564B . . . J OR W PACKAGE
SN74ALS564B . . . DW OR N PACKAGE
(TOP VIEW)
3
2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
2Q
3Q
4Q
5Q
6Q
3D
4D
5D
6D
7D
SN54ALS564B . . . FK PACKAGE
(TOP VIEW)
2D
1D
OE
8Q
7Q
1Q
8D
GND
CLK
V
CC
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN54ALS564B, SN74ALS564B
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS164B APRIL 1982 REVISED JANUARY 1995
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic symbol
logic diagram (positive logic)
OE
1D
2
1D
3
2D
4
3D
5
4D
6
5D
11
CLK
19
18
17
16
15
14
13
12
7
6D
8
7D
9
8D
EN
1
OE
CLK
1D
1Q
1
11
2
19
To Seven Other Channels
C1
1D
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
C1
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
CC
7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, V
I
7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to a disabled 3-state output
5.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
: SN54ALS564B
55
C to 125
C
. . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ALS564B
0
C to 70
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54ALS564B
SN74ALS564B
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
VCC
Supply voltage
4.5
5
5.5
4.5
5
5.5
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.7
0.8
V
IOH
High-level output current
1
2.6
mA
IOL
Low-level output current
12
24
mA
fclock
Clock frequency
0
22
0
30
MHz
tw
Pulse duration, CLK high or low
25
14
ns
tsu
Setup time, data before CLK
15
15
ns
th
Hold time, data after CLK
4
0
ns
TA
Operating free-air temperature
55
125
0
70
C
SN54ALS564B, SN74ALS564B
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS164B APRIL 1982 REVISED JANUARY 1995
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54ALS564B
SN74ALS564B
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
VIK
VCC = 4.5 V,
II = 18 mA
1.2
1.2
V
VCC = 4.5 V to 5.5 V,
IOH = 0.4 mA
VCC 2
VCC 2
VOH
VCC = 4 5 V
IOH = 1 mA
2.4
3.3
V
VCC = 4.5 V
IOH = 2.6 mA
2.4
3.2
VOL
VCC = 4 5 V
IOL = 12 mA
0.25
0.4
0.25
0.4
V
VOL
VCC = 4.5 V
IOL = 24 mA
0.35
0.5
V
IOZH
VCC = 5.5 V,
VO = 2.7 V
20
20
A
IOZL
VCC = 5.5 V,
VO = 0.4 V
20
20
A
II
VCC = 5.5 V,
VI = 7 V
0.1
0.1
mA
IIH
VCC = 5.5 V,
VI = 2.7 V
20
20
A
IIL
VCC = 5.5 V,
VI = 0.4 V
0.2
0.2
mA
IO
VCC = 5.5 V,
VO = 2.25 V
20
112
30
112
mA
Outputs high
10
18
10
18
ICC
VCC = 5.5 V
Outputs low
15
24
15
24
mA
Outputs disabled
16
30
16
30
All typical values are at VCC = 5 V, TA = 25
C.
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
switching characteristics (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
R1 = 500
,
R2 = 500
,
TA = MIN to MAX
UNIT
SN54ALS564B
SN74ALS564B
MIN
MAX
MIN
MAX
fmax
22
30
MHz
tPLH
CLK
An Q
4
24
3
14
ns
tPHL
CLK
Any Q
4
20
4
14
ns
tPZH
OE
An Q
4
24
3
18
ns
tPZL
OE
Any Q
3
23
4
18
ns
tPHZ
OE
Any Q
2
14
1
10
ns
tPLZ
OE
Any Q
3
29
2
15
ns
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
SN54ALS564B, SN74ALS564B
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS164B APRIL 1982 REVISED JANUARY 1995
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/ 74ALS AND 54AS/ 74AS DEVICES
tPHZ
tPLZ
tPHL
tPLH
0.3 V
tPZL
tPZH
tPLH
tPHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
From Output
Under Test
Test
Point
R1
S1
CL
(see Note A)
7 V
1.3 V
1.3 V
1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
1.3 V
1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
High-Level
Pulse
Low-Level
Pulse
tw
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note C)
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
VOL
VOH
VOH
VOL
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
[
0 V
VOH
VOL
[
3.5 V
In-Phase
Output
0.3 V
1.3 V
1.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
R2
VCC
RL
Test
Point
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
From Output
Under Test
Test
Point
CL
(see Note A)
RL
RL = R1 = R2
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR
1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
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Copyright
1998, Texas Instruments Incorporated
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