1
Data sheet acquired from Harris Semiconductor
SCHS204I
Features
Operating Frequency Range
- Up to 18MHz (Typ) at V
CC
= 5V
- Minimum Center Frequency of 12MHz at V
CC
= 4.5V
Choice of Three Phase Comparators
- EXCLUSIVE-OR
- Edge-Triggered JK Flip-Flop
- Edge-Triggered RS Flip-Flop
Excellent VCO Frequency Linearity
VCO-Inhibit Control for ON/OFF Keying and for Low
Standby Power Consumption
Minimal Frequency Drift
Operating Power Supply Voltage Range
- VCO Section . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 6V
- Digital Section . . . . . . . . . . . . . . . . . . . . . . . . 2V to 6V
Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55
o
C to 125
o
C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL
Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
1
A at VOL, VOH
Applications
FM Modulation and Demodulation
Frequency Synthesis and Multiplication
Frequency Discrimination
Tone Decoding
Data Synchronization and Conditioning
Voltage-to-Frequency Conversion
Motor-Speed Control
Description
The 'HC4046A and 'HCT4046A are high-speed silicon-gate
CMOS devices that are pin compatible with the CD4046B of
the "4000B" series. They are specified in compliance with
JEDEC standard number 7.
The 'HC4046A and 'HCT4046A are phase-locked-loop
circuits that contain a linear voltage-controlled oscillator
(VCO) and three different phase comparators (PC1, PC2 and
PC3). A signal input and a comparator input are common to
each comparator.
The signal input can be directly coupled to large voltage
signals, or indirectly coupled (with a series capacitor) to small
voltage signals. A self-bias input circuit keeps small voltage
signals within the linear region of the input amplifiers. With a
passive low-pass filter, the 4046A forms a second-order loop
PLL. The excellent VCO linearity is achieved by the use of
linear op-amp techniques.
Ordering Information
PART NUMBER
TEMP. RANGE
(
o
C)
PACKAGE
CD54HC4046AF3A
-55 to 125
16 Ld CERDIP
CD54HCT4046AF3A
-55 to 125
16 Ld CERDIP
CD74HC4046AE
-55 to 125
16 Ld PDIP
CD74HC4046AM
-55 to 125
16 Ld SOIC
CD74HC4046AMT
-55 to 125
16 Ld SOIC
CD74HC4046AM96
-55 to 125
16 Ld SOIC
CD74HC4046ANSR
-55 to 125
16 Ld SOP
CD74HC4046APWR
-55 to 125
16 Ld TSSOP
CD74HC4046APWT
-55 to 125
16 Ld TSSOP
CD74HCT4046AE
-55 to 125
16 Ld PDIP
CD74HCT4046AM
-55 to 125
16 Ld SOIC
CD74HCT4046AMT
-55 to 125
16 Ld SOIC
CD74HCT4046AM96
-55 to 125
16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
February 1998 - Revised October 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
2003, Texas Instruments Incorporated
CD54HC4046A, CD74HC4046A,
CD54HCT4046A, CD74HCT4046A
High-Speed CMOS Logic
Phase-Locked Loop with VCO
[ /Title
(CD74
HC404
6A,
CD74
HCT40
46A)
/Sub-
ject
(High-
Speed
CMOS
2
Pinout
CD54HC4046A, CD54HCT4046A (CERDIP)
CD74HC4046A (PDIP, SOIC, SOP, TSSOP)
CD74HCT4046A (PDIP, SOIC)
TOP VIEW
Functional Diagram
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
PCP
OUT
PC1
OUT
COMP
IN
VCO
OUT
INH
C1
A
GND
C1
B
V
CC
SIG
IN
PC2
OUT
R
2
R
1
DEM
OUT
VCO
IN
PC3
OUT
10
4
VCO
OUT
DEM
OUT
5
6
7
12
C1
A
R
1
VCO
IN
INH
9
11
C1
B
R
2
15
1
13
2
PC1
OUT
PC3
OUT
PC2
OUT
PCP
OUT
14
3
COMP
IN
SIG
IN
VCO
Pin Descriptions
PIN NUMBER
SYMBOL
NAME AND FUNCTION
1
PCP
OUT
Phase Comparator Pulse Output
2
PC1
OUT
Phase Comparator 1 Output
3
COMP
IN
Comparator Input
4
VCO
OUT
VCO Output
5
INH
Inhibit Input
6
C1
A
Capacitor C1 Connection A
7
C1
B
Capacitor C1 Connection B
8
GND
Ground (0V)
9
VCO
IN
VCO Input
10
DEM
OUT
Demodulator Output
11
R
1
Resistor R1 Connection
12
R
2
Resistor R2 Connection
13
PC2
OUT
Phase Comparator 2 Output
14
SIG
IN
Signal Input
15
PC3
OUT
Phase Comparator 3 Output
16
V
CC
Positive Supply Voltage
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
3
General Description
VCO
The VCO requires one external capacitor C1 (between C1
A
and C1
B
) and one external resistor R1 (between R
1
and
GND) or two external resistors R1 and R2 (between R
1
and
GND, and R
2
and GND). Resistor R1 and capacitor C1
determine the frequency range of the VCO. Resistor R2
enables the VCO to have a frequency offset if required. See
logic diagram, Figure 1.
The high input impedance of the VCO simplifies the design
of low-pass filters by giving the designer a wide choice of
resistor/capacitor ranges. In order not to load the low-pass
filter, a demodulator output of the VCO input voltage is
provided at pin 10 (DEM
OUT
). In contrast to conventional
techniques where the DEM
OUT
voltage is one threshold
voltage lower than the VCO input voltage, here the DEM
OUT
voltage equals that of the VCO input. If DEM
OUT
is used, a
load resistor (R
S
) should be connected from DEM
OUT
to
GND; if unused, DEM
OUT
should be left open. The VCO
output (VCO
OUT
) can be connected directly to the
comparator input (COMP
IN
), or connected via a frequency-
divider. The VCO output signal has a specified duty factor of
50%. A LOW level at the inhibit input (INH) enables the VCO
and demodulator, while a HIGH level turns both off to
minimize standby power consumption.
Phase Comparators
The signal input (SIG
IN
) can be directly coupled to the self-
biasing amplifier at pin 14, provided that the signal swing is
between
the
standard
HC
family
input
logic
levels.
Capacitive coupling is required for signals with smaller
swings.
Phase Comparator 1 (PC1)
This is an Exclusive-OR network. The signal and comparator
input frequencies (f
i
) must have a 50% duty factor to obtain
the maximum locking range. The transfer characteristic of
PC1, assuming ripple (f
r
= 2f
i
) is suppressed, is:
V
DEMOUT
= (V
CC
/
) (
SIG
IN
-
COMP
IN
) where V
DEMOUT
is the demodulator output at pin 10; V
DEMOUT
= V
PC1OUT
(via low-pass filter).
The average output voltage from PC1, fed to the VCO input
via the low-pass filter and seen at the demodulator output at
pin 10 (V
DEMOUT
), is the resultant of the phase differences
of signals (SIG
IN
) and the comparator input (COMP
IN
) as
shown in Figure 2. The average of V
DEM
is equal to 1/2
V
CC
when there is no signal or noise at SIG
IN
, and with this
input the VCO oscillates at the center frequency (f
o
).
Typical waveforms for the PC1 loop locked at f
o
are shown
in Figure 3.
FIGURE 1. LOGIC DIAGRAM
DEM
OUT
R2
12
R1
R5
11
10
C1
R3
C2
PC2
OUT
13
p
n
GND
V
CC
PCP
OUT
1
15
2
PC3
OUT
PC1
OUT
DOWN
R
D
Q
Q
D
CP
R
D
Q
Q
D
CP
UP
V
CC
V
CC
R
D
Q
Q
S
D
INH
5
9
VCO
IN
VCO
-
+
VCO
OUT
COMP
IN
-
+
SIG
IN
C1
B
C1
A
V
REF
R2
R1
6
7 4
3
14
-
+
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
4
The frequency capture range (2f
C
) is defined as the
frequency range of input signals on which the PLL will lock if
it was initially out-of-lock. The frequency lock range (2f
L
) is
defined as the frequency range of input signals on which the
loop will stay locked if it was initially in lock. The capture
range is smaller or equal to the lock range.
With PC1, the capture range depends on the low-pass filter
characteristics and can be made as large as the lock range.
This configuration retains lock behavior even with very noisy
input signals. Typical of this type of phase comparator is that
it can lock to input frequencies close to the harmonics of the
VCO center frequency.
Phase Comparator 2 (PC2)
This is a positive edge-triggered phase and frequency
detector. When the PLL is using this comparator, the loop
is controlled by positive signal transitions and the duty
factors of SIG
IN
and COMP
IN
are not important. PC2
comprises two D-type flip-flops, control-gating and a three-
state output stage. The circuit functions as an up-down
counter (Figure 1) where SIG
IN
causes an up-count and
COMP
IN
a down-count. The transfer function of PC2,
assuming ripple (f
r
= f
i
) is suppressed, is:
V
DEMOUT
=
(V
CC
/4
)
(
SIG
IN
-
COMP
IN
)
where
V
DEMOUT
is
the
demodulator
output
at
pin
10;
V
DEMOUT
=
V
PC2OUT
(via
low-pass
filter).
The average output voltage from PC2, fed to the VCO via the
low-pass filter and seen at the demodulator output at pin 10
(V
DEMOUT
), is the resultant of the phase differences of
SIG
IN
and COMP
IN
as shown in Figure 4. Typical waveforms
for the PC2 loop locked at f
o
are shown in Figure 5.
When the frequencies of SIG
IN
and COMP
IN
are equal but
the phase of SIG
IN
leads that of COMP
IN
, the p-type output
driver at PC2
OUT
is held "ON" for a time corresponding to
the phase difference (
DEMOUT
). When the phase of SIG
IN
lags that of COMP
IN
, the n-type driver is held "ON".
When the frequency of SIG
IN
is higher than that of
COMP
IN
, the p-type output driver is held "ON" for most of
the input signal cycle time, and for the remainder of the
cycle both n- and p-type drivers are "OFF" (three-state). If
the SIG
IN
frequency is lower than the COMP
IN
frequency,
then it is the n-type driver that is held "ON" for most of the
cycle. Subsequently, the voltage at the capacitor (C2) of
the low-pass filter connected to PC2
OUT
varies until the
signal and comparator inputs are equal in both phase and
FIGURE 2. PHASE COMPARATOR 1: AVERAGE OUTPUT
VOLTAGE vs INPUT PHASE DIFFERENCE:
V
DEMOUT
= V
PC1OUT
= (V
CC
/
) (
SIG
IN
-
COMP
IN
);
DEMOUT
= (
SIG
IN
-
COMP
IN
)
V
CC
V
DEMOUT (AV)
1/2 V
CC
0
0
o
90
o
DEMOUT
180
o
FIGURE 3. TYPICAL WAVEFORMS FOR PLL USING PHASE
COMPARATOR 1, LOOP LOCKED AT f
o
SIG
IN
COMP
IN
VCO
OUT
PC1
OUT
VCO
IN
V
CC
GND
FIGURE 4. PHASE COMPARATOR 2: AVERAGE OUTPUT
VOLTAGE vs INPUT PHASE DIFFERENCE:
V
DEMOUT
= V
PC2OUT
= (V
CC
/4
) (
SIG
IN
-
COMP
IN
);
DEMOUT
= (
SIG
IN
-
COMP
IN
)
V
CC
V
DEMOUT (AV)
1/2 V
CC
0
-360
o
0
o
DEMOUT
360
o
FIGURE 5. TYPICAL WAVEFORMS FOR PLL USING PHASE
COMPARATOR 2, LOOP LOCKED AT f
o
SIG
IN
COMP
IN
VCO
OUT
PC2
OUT
VCO
IN
V
CC
GND
PCP
OUT
HIGH IMPEDANCE OFF - STATE
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
5
frequency. At this stable point the voltage on C2 remains
constant as the PC2 output is in three-state and the VCO
input at pin 9 is a high impedance. Also in this condition,
the signal at the phase comparator pulse output (PCP
OUT
)
is a HIGH level and so can be used for indicating a locked
condition.
Thus, for PC2, no phase difference exists between SIG
IN
and COMP
IN
over the full frequency range of the VCO.
Moreover, the power dissipation due to the low-pass filter is
reduced because both p- and n-type drivers are "OFF" for
most of the signal input cycle. It should be noted that the
PLL lock range for this type of phase comparator is equal to
the capture range and is independent of the low-pass filter.
With no signal present at SIG
IN
, the VCO adjusts, via PC2,
to its lowest frequency.
Phase Comparator 3 (PC3)
This
is
a
positive
edge-triggered
sequential
phase
detector using an RS-type flip-flop. When the PLL is using
this comparator, the loop is controlled by positive signal
transitions and the duty factors of SIG
IN
and COMP
IN
are
not
important.
The
transfer
characteristic
of
PC3,
assuming ripple (f
r
= f
i
) is suppressed, is:
V
DEMOUT
=
(V
CC
/2p)
(fSIG
IN
-
fCOMP
IN
)
where
V
DEMOUT
is the demodulator output at pin 10; V
DEMOUT
= V
PC3OUT
(via low-pass filter).
The average output from PC3, fed to the VCO via the low-
pass filter and seen at the demodulator at pin 10
(V
DEMOUT
), is the resultant of the phase differences of
SIG
IN
and COMP
IN
as shown in Figure 6. Typical
waveforms for the PC3 loop locked at f
o
are shown in
Figure 7.
The
phase-to-output
response
characteristic
of
PC3
(Figure 6) differs from that of PC2 in that the phase angle
between SIG
IN
and COMP
IN
varies between 0
o
and 360
o
and is 180
o
at the center frequency. Also PC3 gives a
greater voltage swing than PC2 for input phase differences
but as aconsequence the ripple content of the VCO input
signal is higher. With no signal present at SIG
IN
, the VCO
adjusts, via PC3, to its highest frequency.
The only difference between the HC and HCT versions is the
input level specification of the INH input. This input disables
the VCO section. The comparator's sections are identical, so
that there is no difference in the SIG
IN
(pin 14) or COMP
IN
(pin 3) inputs between the HC and the HCT versions.
FIGURE 6. PHASE COMPARATOR 3: AVERAGE OUTPUT
VOLTAGE vs INPUT PHASE DIFFERENCE:
V
DEMOUT
= V
PC3OUT
= (V
CC
/2
) (
SIG
IN
-
COMP
IN
);
DEMOUT
= (
SIG
IN
-
COMP
IN
)
V
CC
V
DEMOUT (AV)
1/2 V
CC
0
0
o
180
o
DEMOUT
360
o
FIGURE 7. TYPICAL WAVEFORMS FOR PLL USING PHASE
COMPARATOR 3, LOOP LOCKED AT f
o
SIG
IN
COMP
IN
VCO
OUT
PC3
OUT
VCO
IN
V
CC
GND
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
6
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For V
I
< -0.5V or V
I
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . . . .
20mA
DC Output Diode Current, I
OK
For V
O
< -0.5V or V
O
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
20mA
DC Drain Current, per Output, I
O
For -0.5V < V
O
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . . . . . . . .
25mA
DC Output Source or Sink Current per Output Pin, I
O
For V
O
> -0.5V or V
O
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
25mA
DC V
CC
or Ground Current, I
CC
. . . . . . . . . . . . . . . . . . . . . . . . .
50mA
Operating Conditions
Temperature Range, T
A
. . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V
I
, V
O
. . . . . . . . . . . . . . . . . 0V to V
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Package Thermal Impedance,
JA
(see Note 1):
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
o
C/W
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
o
C/W
NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
o
C/W
PW (TSSOP) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 108
o
C/W
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HC TYPES
VCO SECTION
INH High Level Input
Voltage
V
IH
-
-
3
2.1
-
-
2.1
-
2.1
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
INH Low Level Input
Voltage
V
IL
-
-
3
-
-
0.9
-
0.9
-
0.9
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
VCO
OUT
High Level
Output Voltage
CMOS Loads
V
OH
V
IH
or V
IL
-0.02
3
2.9
-
-
2.9
-
2.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
VCO
OUT
High Level
Output Voltage
TTL Loads
-
-
-
-
-
-
-
-
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
-5.2
6
5.48
-
-
5.34
-
5.2
-
V
VCO
OUT
Low Level
Output Voltage
CMOS Loads
V
OL
V
IH
or V
IL
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
VCO
OUT
Low Level
Output Voltage
TTL Loads
-
-
-
-
-
-
-
-
-
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
5.2
6
-
-
0.26
-
0.33
-
0.4
V
C1A, C1B Low Level
Output Voltage
(Test Purposes Only)
V
OL
V
IL
or V
IH
4
4.5
-
-
0.40
-
0.47
-
0.54
V
5.2
6
-
-
0.40
-
0.47
-
0.54
V
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
7
INH VCO
IN
Input
Leakage Current
I
I
V
CC
or
GND
-
6
-
-
0.1
-
1
-
1
A
R1 Range (Note 2)
-
-
-
4.5
3
-
300
-
-
-
-
k
R2 Range (Note 2)
-
-
-
4.5
3
-
300
-
-
-
-
k
C1 Capacitance
Range
-
-
-
3
-
-
No
Limit
-
-
-
-
pF
4.5
-
-
-
-
-
-
pF
6
-
-
-
-
-
-
pF
VCO
IN
Operating
Voltage Range
-
Over the range
specified for R1 for
Linearity See Figure
10, and 35 - 38
(Note 3)
3
1.1
-
1.9
-
-
-
-
V
4.5
1.1
-
3.2
-
-
-
-
V
6
1.1
-
4.6
-
-
-
-
V
PHASE COMPARATOR SECTION
SIG
IN
, COMP
IN
DC Coupled
High-Level Input
Voltage
V
IH
-
-
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
SIG
IN
, COMP
IN
DC Coupled
Low-Level Input
Voltage
V
IL
-
-
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
PCP
OUT
, PCn OUT
High-Level Output
Voltage
CMOS Loads
V
OH
V
IL
or V
IH
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
4.5
4.4
-
-
4.4
-
4.4
-
V
6
5.9
-
-
5.9
-
5.9
-
V
PCP
OUT
, PCn OUT
High-Level Output
Voltage
TTL Loads
V
OH
V
IL
or V
IH
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
-5.2
6
5.48
-
-
5.34
-
5.2
-
V
PCP
OUT
, PCn OUT
Low-Level Output
Voltage
CMOS Loads
V
OL
V
IL
or V
IH
0.02
2
-
-
0.1
-
0.1
-
0.1
V
4.5
-
-
0.1
-
0.1
-
0.1
V
6
-
-
0.1
-
0.1
-
0.1
V
PCP
OUT
, PCn OUT
Low-Level Output
Voltage
TTL Loads
V
OL
V
IL
or V
IH
4
4.5
-
-
0.26
-
0.33
-
0.4
V
5.2
6
-
-
0.26
-
0.33
-
0.4
V
SIG
IN
, COMP
IN
Input
Leakage Current
I
I
V
CC
or
GND
-
2
-
-
3
-
4
-
5
A
3
-
-
7
-
9
-
11
A
4.5
-
-
18
-
23
-
29
A
6
-
-
30
-
38
-
45
A
PC2
OUT
Three-State
Off-State Current
I
OZ
V
IL
or V
IH
-
6
-
-
0.5
-
5
-
10
A
SIG
IN
, COMP
IN
Input
Resistance
R
I
V
I
at Self-Bias
Operation Point:
V
I
= 0.5V,
See Figure 10
3
-
800
-
-
-
-
-
k
4.5
-
250
-
-
-
-
-
k
6
-
150
-
-
-
-
-
k
DEMODULATOR SECTION
Resistor Range
R
S
at R
S
> 300k
Leakage Current
Can Influence
V
DEMOUT
3
50
-
300
-
-
-
-
k
4.5
50
-
300
-
-
-
-
k
6
50
-
300
-
-
-
-
k
DC Electrical Specifications
(Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
8
Offset Voltage VCO
IN
to V
DEM
V
OFF
V
I
= V
VCO IN
=
Values Taken Over
R
S
Range
See Figure 24
3
-
30
-
-
-
-
-
mV
4.5
-
20
-
-
-
-
-
mV
6
-
10
-
-
-
-
-
mV
Dynamic Output
Resistance at
DEM
OUT
R
D
V
DEMOUT
=
3
-
25
-
-
-
-
-
4.5
-
25
-
-
-
-
-
6
-
25
-
-
-
-
-
Quiescent Device
Current
I
CC
Pins 3, 5 and 14
at V
CC
Pin 9 at
GND, I
1
at Pins 3
and 14 to be
excluded
6
-
-
8
-
80
-
160
A
HCT TYPES
VCO SECTION
INH High Level Input
Voltage
V
IH
-
-
4.5 to
5.5
2
-
-
2
-
2
-
V
INH Low Level Input
Voltage
V
IL
-
-
4.5 to
5.5
-
-
0.8
-
0.8
-
0.8
V
VCO
OUT
High Level
Output Voltage
CMOS Loads
V
OH
V
IH
or V
IL
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
VCO
OUT
High Level
Output Voltage
TTL Loads
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
VCO
OUT
Low Level
Output Voltage
CMOS Loads
V
OL
V
IH
or V
IL
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
VCO
OUT
Low Level
Output Voltage
TTL Loads
4
4.5
-
-
0.26
-
0.33
-
0.4
V
C1A, C1B Low Level
Output Voltage
(Test Purposes Only)
V
OL
V
IH
or V
IL
4
4.5
-
-
0.40
-
0.47
-
0.54
V
INH VCO
IN
Input
Leakage Current
I
I
Any Voltage
Between V
CC
and
GND
5.5
-
0.1
-
1
-
1
A
R1 Range (Note 2)
-
-
-
4.5
3
-
300
-
-
-
-
k
R2 Range (Note 2)
-
-
-
4.5
3
-
300
-
-
-
-
k
C1 Capacitance
Range
-
-
-
4.5
0
-
No
Limit
-
-
-
-
pF
VCO
IN
Operating
Voltage Range
-
Over the range
specified for R1 for
Linearity See Figure
10, and 35 - 38
(Note 3)
4.5
1.1
-
3.2
-
-
-
-
V
PHASE COMPARATOR SECTION
SIG
IN
, COMP
IN
DC Coupled
High-Level Input
Voltage
V
IH
-
-
4.5 to
5.5
2
-
-
2
-
2
-
V
DC Electrical Specifications
(Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
V
CC
2
V
CC
2
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
9
SIG
IN
, COMP
IN
DC Coupled
Low-Level Input
Voltage
V
IL
-
-
4.5 to
5.5
-
-
0.8
-
0.8
-
0.8
V
PCP
OUT
, PCn OUT
High-Level Output
Voltage
CMOS Loads
V
OH
V
IL
or V
IH
-
4.5
4.4
-
-
4.4
-
4.4
-
V
PCP
OUT
, PCn OUT
High-Level Output
Voltage
TTL Loads
V
OH
V
IL
or V
IH
-
4.5
3.98
-
-
3.84
-
3.7
-
V
PCP
OUT
, PCn OUT
Low-Level Output
Voltage
CMOS Loads
V
OL
V
IL
or V
IH
-
4.5
-
-
0.1
-
0.1
-
0.1
V
PCP
OUT
, PCn OUT
Low-Level Output
Voltage
TTL Loads
V
OL
V
IL
or V
IH
-
4.5
-
-
0.26
-
0.33
-
0.4
V
SIG
IN
, COMP
IN
Input
Leakage Current
I
I
Any
Voltage
Between
V
CC
and
GND
-
5.5
-
-
30
38
45
A
PC2
OUT
Three-State
Off-State Current
I
OZ
V
IL
or V
IH
-
5.5
-
-
0.5
5
-
-
10
A
SIG
IN
, COMP
IN
Input
Resistance
R
I
V
I
at Self-Bias
Operation Point:
V
I
= 0.5V,
See Figure 10
4.5
-
250
-
-
-
-
-
k
DEMODULATOR SECTION
Resistor Range
R
S
at R
S
> 300k
Leakage Current
Can Influence
V
DEM OUT
4.5
5
-
300
-
-
-
-
k
Offset Voltage VCO
IN
to V
DEM
V
OFF
V
I
= V
VCO IN
=
Values taken over
R
S
Range
See Figure 24
4.5
-
20
-
-
-
-
-
mV
Dynamic Output
Resistance at
DEM
OUT
R
D
V
DEM OUT
=
4.5
-
25
-
-
-
-
-
Quiescent Device
Current
I
CC
V
CC
or
GND
-
5.5
-
-
8
-
80
-
160
A
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
I
CC
(Note 4)
V
CC
-2.1
Excluding
Pin 5
-
4.5 to
5.5
-
100
360
-
450
-
490
A
NOTES:
2. The value for R1 and R2 in parallel should exceed 2.7k
.
3. The maximum operating voltage can be as high as V
CC
-0.9V, however, this may result in an increased offset voltage.
4. For dual-supply systems theoretical worst case (V
I
= 2.4V, V
CC
= 5.5V) specification is 1.8mA.
DC Electrical Specifications
(Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
V
CC
2
V
CC
2
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
10
HCT Input Loading Table
INPUT
UNIT LOADS
INH
1
NOTE: Unit load is
I
CC
limit specific in DC Electrical Specifications
Table, e.g., 360
A max. at 25
o
C.
Switching Specifications
C
L
= 50pF, Input t
r
, t
f
= 6ns
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO
85
o
C
-55
o
C TO
125
o
C
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HC TYPES
PHASE COMPARATOR SECTION
Propagation Delay
t
PLH
, t
PHL
SIG
IN
, COMP
IN
to PCI
OUT
2
-
-
200
-
250
-
300
ns
4.5
-
-
40
-
50
-
60
ns
6
-
-
34
-
43
-
51
ns
SIG
IN
, COMP
IN
to PCP
OUT
2
-
-
300
-
375
-
450
ns
4.5
-
-
60
-
75
-
90
ns
6
-
-
51
-
64
-
77
ns
SIG
IN
, COMP
IN
to PC3
OUT
2
-
-
245
-
305
-
307
ns
4.5
-
-
49
-
61
-
74
ns
6
-
-
42
-
52
-
63
ns
Output Transition Time
t
THL
, t
TLH
2
-
-
75
-
95
-
110
ns
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
Output Enable Time, SIG
IN
,
COMP
IN
to PC2
OUT
t
PZH
, t
PZL
2
-
-
265
-
330
-
400
ns
4.5
-
-
53
-
66
-
80
ns
6
-
-
45
-
56
-
68
ns
Output Disable Time, SIG
IN
,
COMP
IN
to PC2
OUT
t
PHZ
, t
PLZ
2
-
-
315
-
395
-
475
ns
4.5
-
-
63
-
79
-
95
ns
6
-
-
54
-
67
-
81
ns
AC Coupled Input Sensitivity
(
P-P
) at SIG
IN
or COMP
IN
V
I(P-P)
3
-
11
-
-
-
-
-
mV
4.5
-
15
-
-
-
-
-
mV
6
-
33
-
-
-
-
-
mV
VCO SECTION
Frequency Stability with
Temperature Change
f
T
R
1
= 100k
,
R
2
=
3
-
-
TYP
0.11
-
-
%/
o
C
4.5
-
-
-
-
%/
o
C
6
-
-
-
-
%/
o
C
Maximum Frequency
f
MAX
C
1
= 50pF
R
1
= 3.5k
R
2
=
3
-
24
-
-
-
-
-
MHz
4.5
-
24
-
-
-
-
-
MHz
6
-
24
-
-
-
-
-
MHz
C
1
= 0pF
R
1
= 9.1k
R
2
=
3
-
38
-
-
-
-
-
MHz
4.5
-
38
-
-
-
-
-
MHz
6
-
38
-
-
-
-
-
MHz
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
11
Center Frequency
C
1
= 40pF
R
1
= 3k
R
2
=
VCO
IN
=
VCC/2
3
7
10
-
-
-
-
-
MHz
4.5
12
17
-
-
-
-
-
MHz
6
14
21
-
-
-
-
-
MHz
Frequency Linearity
f
VCO
R
1
= 100k
R
2
=
C
1
= 100pF
3
-
0.4
-
-
-
-
-
%
4.5
-
0.4
-
-
-
-
-
%
6
-
0.4
-
-
-
-
-
%
Offset Frequency
R
2
= 220k
C
1
= 1nF
3
-
400
-
-
-
-
-
kHz
4.5
-
400
-
-
-
-
-
kHz
6
-
400
-
-
-
-
-
kHz
DEMODULATOR SECTION
V
OUT
V
S
f
IN
R
1
= 100k
R
2
=
C
1
= 100pF
R
S
= 10k
R
3
= 100k
C
2
= 100pF
3
-
-
-
-
-
-
-
mV/kHz
4.5
-
330
-
-
-
-
-
mV/kHz
6
-
-
-
-
-
-
-
mV/kHz
HCT TYPES
PHASE COMPARATOR SECTION
Propagation Delay
t
PHL,
t
PLH
SIG
IN
, COMP
IN
to PCI
OUT
C
L
= 50pF
4.5
-
-
45
-
56
-
68
ns
SIG
IN
, COMP
IN
to PCP
OUT
t
PHL,
t
PLH
C
L
= 50pF
4.5
-
-
68
-
85
-
102
ns
SIG
IN
, COMP
IN
to PC3
OUT
t
PHL,
t
PLH
C
L
= 50pF
4.5
-
-
58
-
73
-
87
ns
Output Transition Time
t
TLH
, t
THL
C
L
= 50pF
4.5
-
-
15
-
19
-
22
ns
Output Enable Time, SIG
IN
,
COMP
IN
to PC2
OUT
t
PZH
, t
PZL
C
L
= 50pF
4.5
-
-
60
-
75
-
90
pF
Output Disable Time, SIG
IN
,
COMP
IN
to PCZ
OUT
t
PHZ
, t
PLZ
C
L
= 50pF
4.5
-
-
68
-
85
-
102
pF
AC Coupled Input Sensitivity
(
P-P
) at SIG
IN
or COMP
IN
V
I(P-P)
3
-
11
-
-
-
-
-
mV
4.5
-
15
-
-
-
-
-
mV
6
-
33
-
-
-
-
-
mV
VCO SECTION
Frequency Stability with
Temperature Change
f
T
R
1
= 100k
,
R
2
=
4.5
-
0.11
-
-
-
-
-
%/
o
C
Maximum Frequency
f
MAX
C
1
= 50pF
R
1
= 3.5k
R
2
=
4.5
-
24
-
-
-
-
-
MHz
C
1
= 0pF
R
1
= 9.1k
R
2
=
4.5
-
38
-
-
-
-
-
MHz
Center Frequency
C
1
= 40pF
R
1
= 3k
R
2
=
VCO
IN
=
VCC/2
3
7
10
-
-
-
-
-
MHz
4.5
12
17
-
-
-
-
-
MHz
6
14
21
-
-
-
-
-
MHz
Switching Specifications
C
L
= 50pF, Input t
r
, t
f
= 6ns (Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO
85
o
C
-55
o
C TO
125
o
C
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
12
Frequency Linearity
f
VCO
R
1
= 100k
R
2
=
C
1
= 100pF
4.5
-
0.4
-
-
-
-
-
%
Offset Frequency
R
2
= 220k
C
1
= 1nF
4.5
-
400
-
-
-
-
-
kHz
DEMODULATOR SECTION
V
OUT
V
S
f
IN
R
1
= 100k
R
2
=
C
1
= 100pF
R
S
= 10k
R
3
= 100k
C
2
= 100pF
4.5
-
330
-
-
-
-
-
mV/kHz
Switching Specifications
C
L
= 50pF, Input t
r
, t
f
= 6ns (Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO
85
o
C
-55
o
C TO
125
o
C
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
Test Circuits and Waveforms
FIGURE 8. INPUT TO OUTPUT PROPAGATION DELAYS AND
OUTPUT TRANSITION TIMES
FIGURE 9. THREE STATE ENABLE AND DISABLE TIMES FOR
PC2
OUT
V
S
t
PHL
t
PHL
t
TLH
t
TLH
V
S
SIG
IN
COMP
IN
INPUTS
PCP
OUT
PC1
OUT
PC3
OUT
OUTPUTS
V
S
SIG
IN
t
PZH
V
S
V
S
t
PZH
90%
INPUTS
COMP
IN
INPUTS
PC2
OUT
OUTPUT
t
PZL
t
PZL
10%
Typical Performance Curves
FIGURE 10. TYPICAL INPUT RESISTANCE CURVE AT SIG
IN
,
COMP
IN
FIGURE 11. HC/HCT4046A R1 (MIN) OR R2 (MIN) vs SUPPLY
VOLTAGE (V
CC
)
I
I
V
I
V
I
SELF-BIAS OPERATING POINT
800
700
600
500
400
300
200
100
0
0
1
2
3
4
5
6
SUPPLY VOLTAGE, V
CC
(V)
R1
MIN
OR R2
MIN
(OHMS)
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
13
FIGURE 12. HC4046A TYPICAL CENTER FREQUENCY vs R1,
C1 (V
CC
= 4.5V)
FIGURE 13. HC4046A TYPICAL CENTER FREQUENCY vs R1,
C1 (V
CC
= 6V)
FIGURE 14. HC4046A TYPICAL CENTER FREQUENCY vs R1,
C1 (V
CC
= 3V, R2 = OPEN)
FIGURE 15. HCT4046A TYPICAL CENTER FREQUENCY vs R1,
C1 (V
CC
= 4.5V)
FIGURE 16. HCT4046A TYPICAL CENTER FREQUENCY vs R1,
C1 (V
CC
= 5.5V)
FIGURE 17. HC4046A TYPICAL VCO FREQUENCY vs VCO
IN
(R1 = 1.5M
, C1 = 50pF)
Typical Performance Curves
(Continued)
10
8
10
7
10
6
10
5
10
4
10
3
10
2
10
1
1
10
10
2
10
3
10
4
10
5
10
6
CAPACITANCE, C1 (pF)
CENTER FREQ
UENCY (Hz)
VCO
IN
= 0.5 V
CC
V
CC
= 4.5V
R1 = 2.2K
R1 = 22K
R1 = 220K
R1 = 2.2M
R1 = 11M
10
8
10
7
10
6
10
5
10
4
10
3
10
2
10
1
1
10
10
2
10
3
10
4
10
5
10
6
CAPACITANCE, C1 (pF)
CENTER FREQ
UENCY (Hz)
VCO
IN
= 0.5 V
CC
V
CC
= 6.0V
R1 =3K
R1 = 30K
R1 =330K
R1 = 3M
R1 = 15M
10
8
10
7
10
6
10
5
10
4
10
3
10
2
10
1
1
10
10
2
10
3
10
4
10
5
10
6
CAPACITANCE, C1 (pF)
CENTER FREQ
UENCY (Hz)
VCO
IN
= 0.5 V
CC
V
CC
= 3.0V
R2 = OPEN
R1 = 1.5K
R1 = 15K
R1 = 150K
R1 = 1.5M
R1 = 7.5M
10
8
10
7
10
6
10
5
10
4
10
3
10
2
10
1
1
10
10
2
10
3
10
4
10
5
10
6
CAPACITANCE, C1 (pF)
CENTER FREQ
UENCY (Hz)
VCO
IN
= 0.5 V
CC
V
CC
= 4.5V
R1 = 2.2K
R1 = 22K
R1 = 220K
R1 = 2.2M
R1 = 11M
10
8
10
7
10
6
10
5
10
4
10
3
10
2
10
1
1
10
10
2
10
3
10
4
10
5
10
6
CAPACITANCE, C1 (pF)
CENTER FREQ
UENCY (Hz)
VCO
IN
= 0.5 V
CC
V
CC
= 5.5V
R1 = 3K
R1 = 30K
R1 = 300K
R1 = 3M
R1 = 15M
140
120
100
80
60
40
20
0
1
2
3
4
5
6
VCO
IN
(V)
VCO FREQ
UENCY (kHz)
C1 = 50pF
R1 = 1.5M
V
CC
= 3V
V
CC
= 4.5V
V
CC
= 6V
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
14
FIGURE 18. HC4046A TYPICAL VCO FREQUENCY vs VCO
IN
(R1 = 1.5M
, C1 = 0.1
F)
FIGURE 19. HC4046A TYPICAL VCO FREQUENCY vs VCO
IN
(R1 = 150k
, C1 = 0.1
F)
FIGURE 20. HC4046A TYPICAL VCO FREQUENCY vs VCO
IN
(R1 = 5.6k
, C1 = 0.1
F)
FIGURE 21. HC4046A TYPICAL VCO FREQUENCY vs VCO
IN
(R1 = 150k
, C1 = 50pF)
FIGURE 22. HC4046A TYPICAL VCO FREQUENCY vs VCO
IN
(R1 = 5.6k
, C1 = 50pF)
FIGURE 23. HC4046A TYPICAL CHANGE IN VCO FREQUENCY
vs AMBIENT TEMPERATURE AS A FUNCTION OF
R1 (V
CC
= 3V)
Typical Performance Curves
(Continued)
90
70
60
50
40
30
20
10
0
1
2
3
4
5
6
VCO
IN
(V)
VCO FREQ
UENCY (Hz)
C1 = 0.1
F
R1 = 1.5M
V
CC
= 3V
V
CC
= 4.5V
V
CC
= 6V
80
800
600
500
400
300
200
100
0
1
2
3
4
5
6
VCO
IN
(V)
VCO FREQ
UENCY (Hz)
C1 = 0.1
F
R1 = 150K
V
CC
= 3V
V
CC
= 4.5V
V
CC
= 6V
700
18
14
12
10
8
6
4
2
0
1
2
3
4
5
6
VCO
IN
(V)
VCO FREQ
UENCY (kHz)
C1 = 0.1
F
R1 = 5.6k
V
CC
= 3V
V
CC
= 4.5V
V
CC
= 6V
16
1400
1000
800
600
400
200
0
1
2
3
4
5
6
VCO
IN
(V)
VCO FREQ
UENCY (kHz)
C1 = 50pF
R1 = 150K
V
CC
= 3V
V
CC
= 4.5V
V
CC
= 6V
1200
20
16
12
8
4
0
1
2
3
4
5
6
VCO
IN
(V)
VCO FREQ
UENCY (MHz)
C1 = 50pF
R1 = 5.6K
V
CC
= 3V
V
CC
= 4.5V
V
CC
= 6V
24
R1 = 1.5M
R1 = 150K
R1 = 3K
R1 = 1.5K
VCO
IN
= 0.5 V
CC
C1 = 50pF, V
CC
= 3V
R2 = OPEN
24
16
12
8
4
0
-4
VCO FREQ
UENCY CHANGE,
f (%)
20
-75
-50
-25
0
25
50
75
AMBIENT TEMPERATURE, T
A
(
o
C)
100
125
150
-8
-12
-16
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
15
FIGURE 24. HC4046A TYPICAL CHANGE IN VCO FREQUENCY
vs AMBIENT TEMPERATURE AS A FUNCTION OF
R1 (V
CC
= 4.5V)
FIGURE 25. HC4046A TYPICAL CHANGE IN VCO FREQUENCY
vs AMBIENT TEMPERATURE AS A FUNCTION OF
R1 (V
CC
= 6V)
FIGURE 26. HCT4046A TYPICAL CHANGE IN VCO
FREQUENCY vs AMBIENT TEMPERATURE AS A
FUNCTION OF R1
FIGURE 27. HC4046A TYPICAL CHANGE IN VCO FREQUENCY
vs AMBIENT TEMPERATURE AS A FUNCTION OF
R1 (V
CC
= 4.5V)
Typical Performance Curves
(Continued)
R1 = 2.2M
R1 = 220K
R1 = 2.2K
VCO
IN
= 0.5 V
CC
C1 = 50pF, V
CC
= 4.5V
R2 = OPEN
16
12
8
4
0
VCO FREQ
UENCY CHANGE,
f (%)
20
-75
-50
-25
0
25
50
75
AMBIENT TEMPERATURE, T
A
(
o
C)
100
125
150
-4
-8
-12
R1 = 3M
R1 = 300K
R1 = 3K
VCO
IN
= 0.5 V
CC
C1 = 50pF, V
CC
= 6.0V
R2 = OPEN
16
12
8
4
0
VCO FREQ
UENCY CHANGE,
f (%)
-75
-50
-25
0
25
50
75
AMBIENT TEMPERATURE, T
A
(
o
C)
100
125
150
-4
-8
-12
R1 = 3M
R1 = 300K
R1 = 3K
VCO
IN
= 0.5 V
CC
C1 = 50pF, V
CC
= 5.5V
R2 = OPEN
16
12
8
4
0
VCO FREQ
UENCY CHANGE,
f (%)
20
-75
-50
-25
0
25
50
75
AMBIENT TEMPERATURE, T
A
(
o
C)
100
125
150
-4
-8
-12
R1 = 2.2M
R1 = 220K
R1 = 2.2K
VCO
IN
= 0.5 V
CC
C1 = 50pF, V
CC
= 4.5V
R2 = OPEN
16
12
8
4
0
VCO FREQ
UENCY CHANGE,
f (%)
20
-75
-50
-25
0
25
50
75
AMBIENT TEMPERATURE, T
A
(
o
C)
100
125
150
-4
-8
-12
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
16
FIGURE 28. HC4046A OFFSET FREQUENCY vs R2, C1
(V
CC
= 4.5V)
FIGURE 29. HC4046A OFFSET FREQUENCY vs R2, C1
(V
CC
= 3V)
FIGURE 30. HCT4046A OFFSET FREQUENCY vs R2, C1
(V
CC
= 4.5V)
FIGURE 31. HC4046A AND HCT4046A OFFSET FREQUENCY
vs R2, C1 (V
CC
= 6V, V
CC
= 5.5V)
FIGURE 32. HC4046A f
MIN
/f
MAX
vs R2/R1 (V
CC
= 3V, 4.5V, 6V)
FIGURE 33. HCT4046A f
MAX
/f
MIN
vs R2/R1 (V
CC
= 4.5V TO 5.5V)
Typical Performance Curves
(Continued)
R2 = 2.2K
R2 = 22K
R2 = 220K
VCO
IN
= 0.5 V
CC
V
CC
= 4.5V
1
10
10
2
10
3
10
4
10
5
10
6
CAPACITANCE, C1 (pF)
10
8
10
7
10
6
10
5
10
4
10
3
10
2
10
1
OFFSET FREQ
UENCY (Hz)
R2 = 2.2M
R2 = 11M
VCO
IN
= 0.5 V
CC
V
CC
= 3V
1
10
10
2
10
3
10
4
10
5
10
6
CAPACITANCE, C1 (pF)
10
8
10
7
10
6
10
5
10
4
10
3
10
2
10
1
OFFSET FREQ
UENCY (Hz)
R2 = 1.5K
R2 = 15K
R2 = 150K
R2 = 1.5M
R2 = 7.5M
VCO
IN
= 0.5 V
CC
V
CC
= 4.5V
1
10
10
2
10
3
10
4
10
5
10
6
CAPACITANCE, C1 (pF)
10
8
10
7
10
6
10
5
10
4
10
3
10
2
10
1
OFFSET FREQ
UENCY (Hz)
R2 = 2.2K
R2 = 22K
R2 = 220K
R2 = 2.2M
R2 = 11M
1
10
10
2
10
3
10
4
10
5
10
6
CAPACITANCE, C1 (pF)
10
8
10
7
10
6
10
5
10
4
10
3
10
2
10
1
OFFSET FREQ
UENCY (Hz)
R2 = 3K
R2 = 30K
R2 = 300K
R2 = 3M
R2 = 15M
VCO
IN
= 0.5 V
CC
HC V
CC
= 6V
HCT V
CC
= 5.5V
PIN 9 = 0.95 V
CC
FOR f
MAX
PIN 9 = 0V FOR f
MIN
V
CC
= 3V, 4.5V, 6V
10
2
10
f
MAX
/f
MIN
0
10
-2
10
-1
1
R2/R1
10
2
10
PIN 9 = 0.95 V
CC
FOR f
MAX
PIN 9 = 0V FOR f
MIN
V
CC
= 4.5V TO 5.5V
10
2
10
f
MAX
/f
MIN
0
10
-2
10
-1
1
R2/R1
10
2
10
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
17
FIGURE 34. DEFINITION OF VCO FREQUENCY LINEARITY
FIGURE 35. HC4046A VCO LINEARITY vs R1 (V
CC
= 4.5V)
FIGURE 36. HC4046A VCO LINEARITY vs R1 (V
CC
= 3V)
FIGURE 37. HC4046A VCO LINEARITY vs R1 (V
CC
= 6V)
FIGURE 38. HCT4046A VCO LINEARITY vs R1 (V
CC
= 4.5V,
V
CC
= 5.5V)
FIGURE 39. HC4046A DEMODULATOR POWER DISSIPATION
vs RS (TYP) (V
CC
= 3V, 4.5V, 6V)
Typical Performance Curves
(Continued)
f
f
2
f
0
f
0
f
1
V
1/2V
CC
V
VCOIN
MIN
MAX
V
V = 0.5V OVER THE V
CC
RANGE:
FOR VCO LINEARITY
f'
o
= f
1
+ f
2
2
LINEARITY =
f'
o
- f
o
f'
o
x 100%
1K
10K
100K
1M
10M
R1 (OHMS)
8
6
4
2
0
-2
-4
-6
-8
LINEARITY (%)
VCO
IN
= 2.25V
1V
C1 = 50pF
V
CC
= 4.5V
R2 = OPEN
VCO
IN
= 2.25V
0.45V
1K
10K
100K
1M
10M
R1 (OHMS)
8
6
4
2
0
-2
-4
-6
-8
LINEARITY (%)
VCO
IN
= 1.50V
0.4V
C1 = 50pF
V
CC
= 3V
R2 = OPEN
VCO
IN
= 1.50V
0.3V
1K
10K
100K
1M
10M
R1 (OHMS)
8
6
4
2
0
-2
-4
-6
-8
LINEARITY (%)
VCO
IN
= 3V
1.5V
C1 = 50pF
V
CC
= 6V
R2 = OPEN
VCO
IN
= 3V
0.6V
1K
10K
100K
1M
10M
R1 (OHMS)
8
6
4
2
0
-2
-4
-6
-8
LINEARITY (%)
V
CC
= 5.5V,
C1 = 50pF
R2 = OPEN
V
CC
= 4.5V,
VCO
IN
= 2.75V
1.3V
VCO
IN
= 2.25V
1.0V
V
CC
= 5.5V,
V
CC
= 4.5V,
VCO
IN
= 2.75V
0.55V
VCO
IN
= 2.25V
0.45V
VCO
IN
= 0.5 V
CC
1K
10K
100K
1M
RS (OHMS)
10
4
10
3
10
2
10
1
V
CC
= 3V
V
CC
= 4.5V
V
CC
= 6V
DEMODULA
T
OR PO
WER DISSIP
A
TION, P
D
(
W)
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
18
FIGURE 40. HCT4046A DEMODULATOR POWER DISSIPATION
vs RS (TYP) (V
CC
= 3V, 4.5V, 6V)
FIGURE 41. HC4046A VCO POWER DISSIPATION vs R1
(C1 = 50pF, 1
F)
FIGURE 42. HCT4046A VCO POWER DISSIPATION vs R2
(C1 = 50pF, 1
F)
FIGURE 43. HCT4046A VCO POWER DISSIPATION vs R1
(C1 = 50pF, 1
F)
FIGURE 44. HC4046A VCO POWER DISSIPATION vs R2 (C1 = 50pF, 1
F)
Typical Performance Curves
(Continued)
VCO
IN
= 0.5 V
CC
1K
10K
100K
1M
RS (OHMS)
10
4
10
3
10
2
10
1
V
CC
= 3V
V
CC
= 4.5V
V
CC
= 6V
R1 = R2 = OPEN
DEMODULA
T
OR PO
WER DISSIP
A
TION, P
D
(
W)
VCO
IN
= 0.5V
CC
1K
10K
100K
1M
R1 (OHMS)
10
6
10
5
10
4
10
3
10
2
R2 = RS = OPEN
C
L
= 50pF
V
CC
= 6V
C1 = 50pF
V
CC
= 3V
C1 = 1
F
VCO PO
WER DISSIP
A
TION, P
D
(
W)
V
CC
= 6V
C1 = 1
F
V
CC
= 3V
C1 = 50pF
V
CC
= 4.5V
C1 = 1
F
V
CC
= 4.5V
C1 = 50pF
VCO
IN
= 0V (AT f
MIN
)
1K
10K
100K
1M
R2 (OHMS)
10
6
10
5
10
4
10
3
10
2
R1 = RS = OPEN
C
L
= 50pF
V
CC
= 6V
C1 = 50pF
V
CC
= 4.5V
C1 = 1
F
VCO PO
WER DISSIP
A
TION, P
D
(
W)
V
CC
= 4.5V
C1 = 50pF
V
CC
= 6V
C1 = 1
F
VCO
IN
= 0.5V
1K
10K
100K
1M
R1 (OHMS)
10
6
10
5
10
4
10
3
10
2
R2 = RS = OPEN
V
CC
= 5.5V
C1 = 50pF
V
CC
= 5.5V
C1 = 1
F
VCO PO
WER DISSIP
A
TION, P
D
(
W)
V
CC
= 4.5V
C1 = 50pF
V
CC
= 4.5V
C1 = 1
F
VCO
IN
= 0V (AT f
MIN
)
1K
10K
100K
1M
R2 (OHMS)
10
6
10
5
10
4
10
3
10
2
R1 = RS = OPEN
C
L
= 50pF
V
CC
= 6V
C1 = 50pF
V
CC
= 3V
C1 = 1
F
VCO PO
WER DISSIP
A
TION, P
D
(
W)
V
CC
= 4.5V
C1 = 1
F
V
CC
= 4.5V
C1 = 50pF
V
CC
= 6V
C1 = 1
F
V
CC
= 3V
C1 = 50pF
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
19
Application Information
This information is a guide for the approximation of values of
external components to be used with the 'HC4046A and
'HCT4046A in a phase-lock-loop system.
References should be made to Figures 12 through 16 and
Figures 28 through 33 as indicated in the table.
Values of the selected components should be within the
following ranges:
HC/HCT4046A C
PD
CHIP SECTION
HC
HCT
UNIT
Comparator 1
48
50
pF
Comparators 2 and 3
39
48
pF
VCO
61
53
pF
R1
Between 3k
and 300k
R2
Between 3k
and 300k
R1 + R2
Parallel Value > 2.7k
C1
Greater Than 40pF
SUBJECT
PHASE
COMPARATOR
DESIGN CONSIDERATIONS
VCO Frequency
Without Extra Offset
PC1, PC2 or PC3
VCO Frequency Characteristic
With R2 =
and R1 within the range 3k
< R1 < 300k
, the characteristics of the VCO
operation will be as shown in Figures 12 - 16. (Due to R1, C1 time constant a small offset
remains when R2 =
.)
PC1
Selection of R1 and C1
Given f
o
, determine the values of R1 and C1 using Figures 12 - 16.
PC2 or PC3
Given f
MAX
calculate f
o
as f
MAX
/2 and determine the values of R1 and C1 using Figures 12 -
16. To obtain 2f
L
: 2f
L
1.2 (V
CC
- 1.8V)/(R1C1) where valid range of VCO
IN
is 1.1V < VCO
IN
< V
CC
- 0.9V
VCO Frequency with
Extra Offset
PC1, PC2 or PC3
VCO Frequency Characteristic
With R1 and R2 within the ranges 3k
< R1 < 300k
, 3k
, < R2 < 300k
, the characteristics
of the VCO operation will be as shown in Figures 28 - 33.
PC1, PC2 or PC3
Selection of R1, R2 and C1
Given f
o
and f
L
, offset frequency, f
MIN
, may be calculated from f
MIN
f
o
- 1.6 f
L
.
Obtain the values of C1 and R2 by using Figures 28 - 31.
Calculate the values of R1 from Figures 32 - 33.
FIGURE 45. FREQUENCY CHARACTERISTIC OF VCO OPERATING WITHOUT
OFFSET: f
o
= CENTER FREQUENCY: 2f
L
= FREQUENCY LOCK RANGE
f
MAX
f
VCO
f
o
f
MIN
MIN
1/2 V
CC
V
VCOIN
MAX
2f
L
FIGURE 46. FREQUENCY CHARACTERISTIC OF VCO OPERATING WITH OFFSET:
f
o
= CENTER FREQUENCY: 2f
L
= FREQUENCY LOCK RANGE
f
MAX
f
VCO
f
o
f
MIN
MIN
1/2 V
CC
V
VCOIN
MAX
2f
L
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
20
PLL Conditions with
No Signal at the
SIG
IN
Input
PC1
VCO adjusts to f
o
with
DEMOUT
= 90
o
and V
VCOIN
= 1/2 V
CC
(see Figure 2)
PC2
VCO adjusts to f
MIN
with
DEMOUT
= -360
o
and V
VCOIN
= 0V (see Figure 4)
PC3
VCO adjusts to f
MAX
with
DEMOUT
= 360
o
and V
VCOIN
= V
CC
(see Figure 6)
PLL Frequency
Capture Range
PC1, PC2 or PC3
Loop Filter Component Selection
PLL Locks on
Harmonics at Center
Frequency
PC1 or PC3
Yes
PC2
No
Noise Rejection at
Signal Input
PC1
High
PC2 or PC3
Low
AC Ripple Content
when PLL is Locked
PC1
f
r
= 2f
i
, large ripple content at
DEMOUT
= 90
o
PC2
f
r
= f
i
, small ripple content at
DEMOUT
= 0
o
PC3
f
r
= fSIG
IN
, large ripple content at
DEMOUT
= 180
o
SUBJECT
PHASE
COMPARATOR
DESIGN CONSIDERATIONS
A small capture range (2f
c
) is obtained if
> 2f
c
1/
(2
f
L
/
.)
1/2
FIGURE 47. SIMPLE LOOP FILTER FOR PLL WITHOUT OFFSET
(A)
= R3 x C2
(B) AMPLITUDE CHARACTERISTIC
(C) POLE-ZERO DIAGRAM
R3
C2
INPUT
OUTPUT
|F
(j
)
|
-1/
FIGURE 48. SIMPLE LOOP FILTER FOR PLL WITH OFFSET
(A)
1 = R3 x C2;
(B) AMPLITUDE CHARACTERISTIC
(C) POLE-ZERO DIAGRAM
|F
(j
)
|
-1/
2
R3
C2
INPUT
OUTPUT
2 = R4 x C2;
3 = (R3 + R4) x C2
-1/
3
m
1/
3
1/
2
R4
m =
R4
R3 + R4
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
MECHANICAL
MPDI002C JANUARY 1995 REVISED DECEMBER 20002
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
BB
AC
AD
0.325 (8,26)
0.300 (7,62)
0.010 (0,25) NOM
Gauge Plane
0.015 (0,38)
0.430 (10,92) MAX
20
1.060
(26,92)
0.940
(23,88)
18
0.920
0.850
14
0.775
0.745
(19,69)
(18,92)
16
0.775
(19,69)
(18,92)
0.745
A MIN
DIM
A MAX
PINS **
(23,37)
(21,59)
Seating Plane
14/18 PIN ONLY
20 pin vendor option
4040049/E 12/2002
9
8
0.070 (1,78)
A
0.045 (1,14)
0.020 (0,51) MIN
16
1
0.015 (0,38)
0.021 (0,53)
0.200 (5,08) MAX
0.125 (3,18) MIN
0.240 (6,10)
0.260 (6,60)
M
0.010 (0,25)
0.100 (2,54)
16 PINS SHOWN
MS-100
VARIATION
AA
C
D
D
D
0.030 (0,76)
0.045 (1,14)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001, except 18 and 20 pin minimum body lrngth (Dim A).
D. The 20 pin end lead shoulder width is a vendor option, either half or full width.
MECHANICAL DATA
MSOI002B JANUARY 1995 REVISED SEPTEMBER 2001
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
8 PINS SHOWN
8
0.197
(5,00)
A MAX
A MIN
(4,80)
0.189
0.337
(8,55)
(8,75)
0.344
14
0.386
(9,80)
(10,00)
0.394
16
DIM
PINS **
4040047/E 09/01
0.069 (1,75) MAX
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.010 (0,25)
0.016 (0,40)
0.044 (1,12)
0.244 (6,20)
0.228 (5,80)
0.020 (0,51)
0.014 (0,35)
1
4
8
5
0.150 (3,81)
0.157 (4,00)
0.008 (0,20) NOM
0
8
Gage Plane
A
0.004 (0,10)
0.010 (0,25)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
MECHANICAL DATA
MTSS001C JANUARY 1995 REVISED FEBRUARY 1999
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65
M
0,10
0,10
0,25
0,50
0,75
0,15 NOM
Gage Plane
28
9,80
9,60
24
7,90
7,70
20
16
6,60
6,40
4040064/F 01/97
0,30
6,60
6,20
8
0,19
4,30
4,50
7
0,15
14
A
1
1,20 MAX
14
5,10
4,90
8
3,10
2,90
A MAX
A MIN
DIM
PINS **
0,05
4,90
5,10
Seating Plane
0
8
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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