1
Data sheet acquired from Harris Semiconductor
SCHS192B
Features
Buffered Inputs
Three-State Outputs
Applications in Multiple-Data-Bus Architecture
Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55
o
C to 125
o
C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL
Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
1
A at V
OL
, V
OH
Pinout
CD54HC640, CD54HCT640
(CERDIP)
CD74HC640, CD74HCT640
(PDIP, SOIC)
TOP VIEW
Description
The 'HC640 and 'HCT640 silicon-gate CMOS three-state
bidirectional inverting and non-inverting buffers are intended
for two-way asynchronous communication between data
buses. They have high drive current outputs which enable
high-speed operation when driving large bus capacitances.
These circuits possess the low power dissipation of CMOS
circuits, and have speeds comparable to low power Schottky
TTL circuits. They can drive 15 LSTTL loads. The 'HC640
and 'HCT640 are inverting buffers.
The direction of data flow (A to B, B to A) is controlled by the
DIR input.
Outputs are enabled by a low on the Output Enable input
(OE); a high OE puts these devices in the high impedance
mode.
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
DIR
A0
A1
A2
A3
A4
A6
A5
A7
GND
V
CC
B0
B1
B2
OE
B3
B4
B5
B6
B7
Ordering Information
PART NUMBER
TEMP. RANGE
(
o
C)
PACKAGE
CD54HC640F3A
-55 to 125
20 Ld CERDIP
CD54HCT640F3A
-55 to 125
20 Ld CERDIP
CD74HC640E
-55 to 125
20 Ld PDIP
CD74HC640M
-55 to 125
20 Ld SOIC
CD74HCT640E
-55 to 125
20 Ld PDIP
CD74HCT640M
-55 to 125
20 Ld SOIC
January 1998 - Revised May 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
2003, Texas Instruments Incorporated
CD54HC640, CD74HC640,
CD54HCT640, CD74HCT640
High-Speed CMOS Logic
Octal Three-State Bus Transceiver, Inverting
[ /Title
(CD74
HC640
,
CD74
HCT64
0)
/Sub-
ject
(High
Speed
CMOS
2
Functional Diagram
OUTPUT ENABLE AND
DIRECTION-SELECT LOGIC
A0
A7
OE
DIR
B0
B7
A1
THRU
A6
B1
THRU
B6
V
CC
= 20
GND = 10
TRUTH TABLE
CONTROL INPUTS
DATA PORT STATUS
OE
DIR
A
n
B
n
L
L
O
I
H
H
Z
Z
H
L
Z
Z
L
H
I
O
To prevent excess currents in the High-Z modes all I/O terminals
should be terminated with 1k
to 1M
resistors.
H = High Level
L = Low Level
I = Input
O = Output (Inversion of Input Level)
Z = High Impedance
CD54HC640, CD74HC640, CD54HCT640, CD74HCT640
CD54HC640, CD74HC640, CD54HCT640, CD74HCT640
3
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For V
I
< -0.5V or V
I
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . . . .
20mA
DC Output Diode Current, I
OK
For V
O
< -0.5V or V
O
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
20mA
DC Drain Current, per Output, I
O
For -0.5V < V
O
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . . . . . . . .
35mA
DC Output Source or Sink Current per Output Pin, I
O
For V
O
> -0.5V or V
O
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
25mA
DC V
CC
or Ground Current, I
CC
. . . . . . . . . . . . . . . . . . . . . . . . .
50mA
Operating Conditions
Temperature Range, T
A
. . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V
I
, V
O
. . . . . . . . . . . . . . . . . 0V to V
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Thermal Resistance (Typical, Note 1)
JA
(
o
C/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .
69
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .
58
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HC TYPES
High Level Input
Voltage
V
IH
-
-
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
Low Level Input
Voltage
V
IL
-
-
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
High Level Output
Voltage
CMOS Loads
V
OH
V
IH
or V
IL
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-
-
V
-6
4.5
3.98
-
-
3.84
-
3.7
-
V
-7.8
6
5.48
-
-
5.34
-
5.2
-
V
Low Level Output
Voltage
CMOS Loads
V
OL
V
IH
or V
IL
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
Low Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-
-
V
6
4.5
-
-
0.26
-
0.33
-
0.4
V
7.8
6
-
-
0.26
-
0.33
-
0.4
V
Input Leakage
Current
I
I
V
CC
or
GND
-
6
-
-
0.1
-
1
-
1
A
CD54HC640, CD74HC640, CD54HCT640, CD74HCT640
CD54HC640, CD74HC640, CD54HCT640, CD74HCT640
4
Quiescent Device
Current
I
CC
V
CC
or
GND
0
6
-
-
8
-
80
-
160
A
Three-State Leakage
Current
I
OZ
V
IL
or V
IH
V
O
=
V
CC
or
GND
6
-
-
0.5
-
5
-
10
A
HCT TYPES
High Level Input
Voltage
V
IH
-
-
4.5 to
5.5
2
-
-
2
-
2
-
V
Low Level Input
Voltage
V
IL
-
-
4.5 to
5.5
-
-
0.8
-
0.8
-
0.8
V
High Level Output
Voltage
CMOS Loads
V
OH
V
IH
or V
IL
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
High Level Output
Voltage
TTL Loads
-6
4.5
3.98
-
-
3.84
-
3.7
-
V
Low Level Output
Voltage
CMOS Loads
V
OL
V
IH
or V
IL
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
Low Level Output
Voltage
TTL Loads
6
4.5
-
-
0.26
-
0.33
-
0.4
V
Input Leakage
Current
I
I
V
CC
and
GND
0
5.5
-
-
0.1
-
1
-
1
A
Quiescent Device
Current
I
CC
V
CC
or
GND
0
5.5
-
-
8
-
80
-
160
A
Three-State Leakage
Current
I
OZ
V
IL
or V
IH
V
O
=
V
CC
or
GND
5.5
-
-
0.5
-
5
-
10
A
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
I
CC
(Note 2)
V
CC
-2.1
-
4.5 to
5.5
-
100
360
-
450
-
490
A
NOTE:
2. For dual-supply systems theoretical worst case (V
I
= 2.4V, V
CC
= 5.5V) specification is 1.8mA.
DC Electrical Specifications
(Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HCT Input Loading Table
INPUT
UNIT LOADS
DIR
0.9
OE, A
1.5
B
1.5
NOTE: Unit Load is
I
CC
limit specified in DC Electrical Table, e.g.,
360
A max at 25
o
C.
CD54HC640, CD74HC640, CD54HCT640, CD74HCT640
CD54HC640, CD74HC640, CD54HCT640, CD74HCT640
5
Switching Specifications
C
L
= 50pF, Input t
r
, t
f
= 6ns
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO
85
o
C
-55
o
C TO
125
o
C
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HC TYPES
Propagation Delay
t
PHL
, t
PLH
C
L
= 50pF
A to B
B to A
2
-
-
90
-
115
-
135
ns
4.5
-
-
18
-
23
-
27
ns
C
L
= 15pF
5
-
7
-
-
-
-
-
ns
C
L
= 50pF
6
-
-
15
-
20
-
23
ns
Output High-Z
To High Level,
To Low Level
t
PHL,
t
PLH
C
L
= 50pF
2
-
-
150
-
190
-
225
ns
4.5
-
-
30
-
38
-
45
ns
C
L
= 15pF
5
-
12
-
-
-
-
-
ns
C
L
= 50pF
6
-
-
26
-
33
-
38
ns
Output High Level
Output Low Level to High Z
t
PHZ,
t
PLZ
C
L
= 50pF
2
-
-
150
-
190
-
225
ns
4.5
-
-
30
-
38
-
45
ns
C
L
= 15pF
5
-
12
-
-
-
-
-
ns
C
L
= 50pF
6
-
-
26
-
33
-
38
ns
Output Transition Time
t
THL
, t
TLH
C
L
= 50pF
2
-
-
60
-
75
-
90
ns
4.5
-
-
12
-
15
-
18
ns
6
-
-
10
-
13
-
15
ns
Input Capacitance
C
IN
C
L
= 50pF
-
10
-
10
-
10
-
10
pF
Three-State Output
Capacitance
C
O
-
-
-
-
20
-
20
-
20
pF
Power Dissipation Capacitance
(Notes 3, 4)
C
PD
-
5
-
38
-
-
-
-
-
pF
HCT TYPES
Propagation Delay
A to B
B to A
t
PHL,
t
PLH
C
L
= 50pF
4.5
-
-
22
-
28
-
33
ns
C
L
= 15pF
5
-
9
-
-
-
-
-
ns
Output High-Z
To High Level,
To Low Level
t
PHL,
t
PLH
C
L
= 50pF
4.5
-
-
30
-
38
-
45
ns
C
L
= 15pF
5
-
12
-
-
-
-
-
ns
Output High Level
Output Low Level to High Z
t
PHZ,
t
PLZ
C
L
= 50pF
4.5
-
-
30
-
38
-
45
ns
C
L
= 15pF
5
-
12
-
-
-
-
-
ns
Output Transition Time
t
THL
, t
TLH
C
L
= 50pF
4.5
-
-
12
-
15
-
18
ns
Input Capacitance
C
IN
C
L
= 50pF
-
10
-
10
-
10
-
10
pF
Three-State Output
Capacitance
C
O
-
-
-
-
20
-
20
-
20
pF
Power Dissipation Capacitance
(Notes 3, 4)
C
PD
-
5
-
41
-
-
-
-
-
pF
NOTES:
3. C
PD
is used to determine the dynamic power consumption, per channel.
4. P
D
= V
CC
2
f
i
(C
PD
+ C
L
) where f
i
= Input Frequency, C
L
= Output Load Capacitance, V
CC
= Supply Voltage.
CD54HC640, CD74HC640, CD54HCT640, CD74HCT640
CD54HC640, CD74HC640, CD54HCT640, CD74HCT640
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