SN54HC166, SN74HC166
8 BIT PARALLEL LOAD SHIFT REGISTERS
SCLS117D - DECEMBER 1982 - REVISED SEPTEMBER 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Wide Operating Voltage Range of 2 V to 6 V
D
Outputs Can Drive Up To 10 LSTTL Loads
D
Low Power Consumption, 80-
A Max I
CC
D
Typical t
pd
= 13 ns
D
4-mA Output Drive at 5 V
D
Low Input Current of 1
A Max
D
Synchronous Load
D
Direct Overriding Clear
D
Parallel-to-Serial Conversion
3
2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
H
Q
H
NC
G
F
B
C
NC
D
CLK INH
A
SER
NC
CLR
E
V
SH/LD
CLK
GND
NC
SN54HC166 . . . FK PACKAGE
(TOP VIEW)
CC
NC - No internal connection
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SER
A
B
C
D
CLK INH
CLK
GND
V
CC
SH/LD
H
Q
H
G
F
E
CLR
SN54HC166 . . . J OR W PACKAGE
SN74HC166 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
description/ordering information
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP - N
Tube of 25
SN74HC166N
SN74HC166N
Tube of 40
SN74HC166D
SOIC - D
Reel of 2500
SN74HC166DR
HC166
SOIC - D
Reel of 250
SN74HC166DT
HC166
-40
C to 85
C
SOP - NS
Reel of 2000
SN74HC166NSR
HC166
-40 C to 85 C
SSOP - DB
Reel of 2000
SN74HC166DBR
HC166
Tube of 90
SN74HC166PW
TSSOP - PW
Reel of 2000
SN74HC166PWR
HC166
TSSOP - PW
Reel of 250
SN74HC166PWT
HC166
CDIP - J
Tube of 25
SNJ54HC166J
SNJ54HC166J
-55
C to 125
C
CFP - W
Tube of 150
SNJ54HC166W
SNJ54HC166W
-55 C to 125 C
LCCC - FK
Tube of 55
SNJ54HC166FK
SNJ54HC166FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL PRF 38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54HC166, SN74HC166
8 BIT PARALLEL LOAD SHIFT REGISTERS
SCLS117D - DECEMBER 1982 - REVISED SEPTEMBER 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
These parallel-in or serial-in, serial-out registers feature gated clock (CLK, CLK INH) inputs and an overriding
clear (CLR) input. The parallel-in or serial-in modes are established by the shift/ load (SH/LD) input. When high,
SH/LD enables the serial (SER) data input and couples the eight flip-flops for serial shifting with each clock
(CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and synchronous loading occurs on
the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the
low-to-high-level edge of CLK through a 2-input positive-NOR gate, permitting one input to be used as a
clock-enable or clock-inhibit function. Holding either CLK or CLK INH high inhibits clocking; holding either low
enables the other clock input. This allows the system clock to be free running, and the register can be stopped
on command with the other clock input. CLK INH should be changed to the high level only when CLK is high.
CLR overrides all other inputs, including CLK, and resets all flip-flops to zero.
FUNCTION TABLE
INPUTS
OUTPUTS
INPUTS
INTERNAL
CLR
SH/LD
CLK INH
CLK
SER
PARALLEL
A . . . H
QA
QB
QH
L
X
X
X
X
X
L
L
L
H
X
L
L
X
X
QA0
QB0
QH0
H
L
L
X
a . . . h
a
b
h
H
H
L
H
X
H
QAn
QGn
H
H
L
L
X
L
QAn
QGn
H
X
H
X
X
QA0
QB0
QH0
logic diagram (positive logic)
1D
C1
15
9
7
6
13
SH/LD
CLR
CLK
CLK INH
QH
2
3
4
5
10
11
12
14
SER
A
B
C
D
E
F
G
H
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1
Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
SN54HC166, SN74HC166
8 BIT PARALLEL LOAD SHIFT REGISTERS
SCLS117D - DECEMBER 1982 - REVISED SEPTEMBER 2003
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
typical clear, shift, load, inhibit, and shift sequence
Clear
Load
Inhibit
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
CLK
CLK INH
SER
A
B
C
D
E
F
G
H
SH/LD
CLR
QH
Parallel
Inputs
Serial Shift
Serial Shift
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
-0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) (see Note 1)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) (see Note 1)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
25 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): D package
73
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DB package
82
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package
67
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package
64
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package
108
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
-65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
SN54HC166, SN74HC166
8 BIT PARALLEL LOAD SHIFT REGISTERS
SCLS117D - DECEMBER 1982 - REVISED SEPTEMBER 2003
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
SN54HC166
SN74HC166
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
VCC
Supply voltage
2
5
6
2
5
6
V
VCC = 2 V
1.5
1.5
VIH
High-level input voltage
VCC = 4.5 V
3.15
3.15
V
VIH
High-level input voltage
VCC = 6 V
4.2
4.2
V
VCC = 2 V
0.5
0.5
VIL
Low-level input voltage
VCC = 4.5 V
1.35
1.35
V
VIL
Low-level input voltage
VCC = 6 V
1.8
1.8
V
VI
Input voltage
0
VCC
0
VCC
V
VO
Output voltage
0
VCC
0
VCC
V
VCC = 2 V
1000
1000
t/
v
Input transition rise/fall time
VCC = 4.5 V
500
500
ns
t/
v
Input transition rise/fall time
VCC = 6 V
400
400
ns
TA
Operating free-air temperature
-55
125
-40
85
C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced
grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally,
the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
SN54HC166
SN74HC166
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
2 V
1.9
1.998
1.9
1.9
IOH = -20
A
4.5 V
4.4
4.499
4.4
4.4
VOH
VI = VIH or VIL
IOH = -20
A
6 V
5.9
5.999
5.9
5.9
V
VOH
VI = VIH or VIL
IOH = -4 mA
4.5 V
3.98
4.3
3.7
3.84
V
IOH = -5.2 mA
6 V
5.48
5.8
5.2
5.34
2 V
0.002
0.1
0.1
0.1
IOL = 20
A
4.5 V
0.001
0.1
0.1
0.1
VOL
VI = VIH or VIL
IOL = 20
A
6 V
0.001
0.1
0.1
0.1
V
VOL
VI = VIH or VIL
IOL = 4 mA
4.5 V
0.17
0.26
0.4
0.33
V
IOL = 5.2 mA
6 V
0.15
0.26
0.4
0.33
II
VI = VCC or 0
6 V
0.1
100
1000
1000
nA
ICC
VI = VCC or 0,
IO = 0
6 V
8
160
80
A
Ci
2 V to 6 V
3
10
10
10
pF
SN54HC166, SN74HC166
8 BIT PARALLEL LOAD SHIFT REGISTERS
SCLS117D - DECEMBER 1982 - REVISED SEPTEMBER 2003
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
TA = 25
C
SN54HC166
SN74HC166
UNIT
VCC
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
2 V
6
4.2
5
fclock
Clock frequency
4.5 V
31
21
25
MHz
fclock
Clock frequency
6 V
36
25
29
MHz
2 V
100
150
125
CLR low
4.5 V
20
30
25
tw
Pulse duration
CLR low
6 V
17
26
21
ns
tw
Pulse duration
2 V
80
120
100
ns
CLK high or low
4.5 V
16
24
20
CLK high or low
6 V
14
20
17
2 V
145
220
180
SH/LD high before CLK
4.5 V
29
44
36
SH/LD high before CLK
6 V
25
38
31
2 V
80
120
100
SER before CLK
4.5 V
16
24
20
SER before CLK
6 V
14
20
17
2 V
100
150
125
tsu
Setup time
CLK INH low before CLK
4.5 V
20
30
25
ns
tsu
Setup time
CLK INH low before CLK
6 V
17
26
21
ns
2 V
80
120
100
Data before CLK
4.5 V
16
24
20
Data before CLK
6 V
14
20
17
2 V
40
60
50
CLR inactive before CLK
4.5 V
8
12
10
CLR inactive before CLK
6 V
7
10
9
2 V
0
0
0
SH/LD high after CLK
4.5 V
0
0
0
SH/LD high after CLK
6 V
0
0
0
2 V
5
5
5
SER after CLK
4.5 V
5
5
5
th
Hold time
SER after CLK
6 V
5
5
5
ns
th
Hold time
2 V
0
0
0
ns
CLK INH high after CLK
4.5 V
0
0
0
CLK INH high after CLK
6 V
0
0
0
2 V
5
5
5
Data after CLK
4.5 V
5
5
5
Data after CLK
6 V
5
5
5
PDF 
ZIP