SN54BCT540, SN74BCT540A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS012E JULY 1988 REVISED MARCH 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Operating Voltage Range of 4.5 V to 5.5 V
D
State-of-the-Art BiCMOS Design
Significantly Reduces I
CCZ
D
3-State Outputs Drive Bus Lines or Buffer
Memory Address Registers
D
P-N-P Inputs Reduce DC Loading
D
Data Flow-Through Pinout (All Inputs on
Opposite Side From Outputs)
D
ESD Protection Exceeds JESD 22
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)
SN54BCT540 . . . FK PACKAGE
(TOP VIEW)
SN54BCT540 . . . J OR W PACKAGE
SN74BCT540A . . . DW, N, OR NS PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE1
A1
A2
A3
A4
A5
A6
A7
A8
GND
V
CC
OE2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
Y1
Y2
Y3
Y4
Y5
A3
A4
A5
A6
A7
A2
A1
OE1
Y7
Y6
OE2
A8
GND
Y8
V
CC
description/ordering information
The SN54BCT540 and SN74BCT540A octal buffers and line drivers are ideal for driving bus lines or buffer
memory-address registers. The devices feature inputs and outputs on opposite sides of the package to facilitate
printed circuit board layout.
The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1 or OE2)
input is high, all corresponding outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP N
Tube
SN74BCT540AN
SN74BCT540AN
0
C to 70
C
SOIC
DW
Tube
SN74BCT540ADW
BCT540A
0
C to 70
C
SOIC DW
Tape and reel
SN74BCT540ADWR
BCT540A
SOP NS
Tape and reel
SN74BCT540ANSR
BCT540A
CDIP J
Tube
SNJ54BCT540J
SNJ54BCT540J
55
C to 125
C
CFP W
Tube
SNJ54BCT540W
SNJ54BCT540W
LCCC FK
Tube
SNJ54BCT540FK
SNJ54BCT540FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Copyright
2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54BCT540, SN74BCT540A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS012E JULY 1988 REVISED MARCH 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
OUTPUT
OE1
OE2
A
OUTPUT
Y
L
L
L
H
L
L
H
L
H
X
X
Z
X
H
X
Z
logic diagram (positive logic)
1
19
OE1
OE2
A1
2
18
Y1
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the disabled or power-off state, V
O
0.5 V to 5.5 V
. . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state, V
O
0.5 V to V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
30 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the low state: SN54BCT540
96 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74BCT540A 128
mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): DW package
58
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package
69
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package
60
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
SN54BCT540, SN74BCT540A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS012E JULY 1988 REVISED MARCH 2003
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
SN54BCT540
SN74BCT540A
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
VCC
Supply voltage
4.5
5
5.5
4.5
5
5.5
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
IIK
Input clamp current
18
18
mA
IOH
High-level output current
12
15
mA
IOL
Low-level output current
48
64
mA
TA
Operating free-air temperature
55
125
0
70
C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54BCT540
SN74BCT540A
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
VIK
VCC = 4.5 V,
II = 18 mA
1.2
1.2
V
IOH = 3 mA
2.4
3.3
2.4
3.3
VOH
VCC = 4.5 V
IOH = 12 mA
2
3.2
V
IOH = 15 mA
2
3.1
VOL
VCC = 4 5 V
IOL = 48 mA
0.38
0.55
V
VOL
VCC = 4.5 V
IOL = 64 mA
0.42
0.55
V
II
VCC = 5.5 V,
VI = 7 V
0.1
0.1
mA
IIH
VCC = 5.5 V,
VI = 2.7 V
20
20
A
IIL
VCC = 5.5 V,
VI = 0.5 V
0.6
0.6
mA
IOS
VCC = 5.5 V,
VO = 0
100
225
100
225
mA
IOZH
VCC = 5.5 V,
VO = 2.7 V
50
50
A
IOZL
VCC = 5.5 V,
VO = 0.5 V
50
50
A
ICCH
VCC = 5.5 V
20
30
20
30
mA
ICCL
VCC = 5.5 V
45
71
45
71
mA
ICCZ
VCC = 5.5 V
3
6
3
6
mA
Ci
VCC = 5 V,
VI = 2.5 V or 0.5 V
6
5
pF
Co
VCC = 5 V,
VO = 2.5 V or 0.5 V
10
10
pF
All typical values are at VCC = 5 V, TA = 25
C.
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
SN54BCT540, SN74BCT540A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS012E JULY 1988 REVISED MARCH 2003
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
CL = 50 pF,
R1 = 500
,
R2 = 500
,
TA = 25
C
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
R1 = 500
,
R2 = 500
,
TA = MIN to MAX
UNIT
'BCT540
SN54BCT540
SN74BCT540A
MIN
TYP
MAX
MIN
MAX
MIN
MAX
tPLH
A
Y
2.5
4.1
5.8
1.9
7.2
2
6.9
ns
tPHL
A
Y
0.6
1.9
3.5
0.3
4.5
0.3
4
ns
tPZH
OE
Y
4
6.8
8.9
4.1
10.4
3.3
10.1
ns
tPZL
OE
Y
5
8
10
5.3
11.8
4.3
11.3
ns
tPHZ
OE
Y
3.5
5.7
7.8
2.7
9.4
2.7
9
ns
tPLZ
OE
Y
3.8
5.5
7.4
3.5
8.9
3.5
8.5
ns
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
SN54BCT540, SN74BCT540A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS012E JULY 1988 REVISED MARCH 2003
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, tr = tf
2.5 ns, duty cycle = 50%.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
E. When measuring propagation delay times of 3-state outputs, switch S1 is open.
F. All parameters and waveforms are not applicable to all devices.
From Output
Under Test
Test
Point
R1
CL
(see Note A)
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR
3-STATE AND OPEN-COLLECTOR OUTPUTS
R1
S1
7 V (tPZL, tPLZ, O.C.)
Open
(all others)
From Output
Under Test
Test
Point
R2
CL
(see Note A)
RL = R1 = R2
1.5 V
1.5 V
1.5 V
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing Input
(see Note B)
Data Input
(see Note B)
1.5 V
1.5 V
3 V
3 V
0 V
0 V
High-Level
Pulse
(see Note B)
Low-Level
Pulse
tw
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V
1.5 V
tPHL
tPLH
tPLH
tPHL
Input
(see Note B)
Out-of-Phase
Output
(see Note D)
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
3 V
0 V
VOL
VOH
VOH
VOL
In-Phase
Output
(see Note D)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (see Note D)
tPHZ
tPLZ
0.3 V
tPZL
tPZH
1.5 V
1.5 V
1.5 V
1.5 V
3 V
0 V
Output
Control
(low-level enable)
Waveform 1
(see Notes C and D)
Waveform 2
(see Notes C and D)
0 V
VOH
VOL
3.5 V
0.3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
Figure 1. Load Circuit and Voltage Waveforms
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