SN54BCT8245A, SN74BCT8245A

SCAN TEST DEVICES

WITH OCTAL BUS TRANSCEIVERS

SCBS043E MAY 1990 REVISED JULY 1996

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Members of the Texas Instruments
SCOPE

Family of Testability Products

Octal Test-Integrated Circuits

Functionally Equivalent to 'F245 and
'BCT245 in the Normal- Function Mode

Compatible With the IEEE Standard
1149.1-1990 (JTAG) Test Access Port and
Boundary-Scan Architecture

Test Operation Synchronous to Test
Access Port (TAP)

Implement Optional Test Reset Signal by
Recognizing a Double-High-Level Voltage
(10 V ) on TMS Pin

SCOPE

Instruction Set

 IEEE Standard 1149.1-1990 Required

Instructions, Optional INTEST, CLAMP,
and HIGHZ

Parallel-Signature Analysis at Inputs
Pseudo-Random Pattern Generation

From Outputs

 Sample Inputs/Toggle Outputs

Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic
and Ceramic 300-mil DIPs (JT, NT)

description

The 'BCT8245A scan test devices with octal bus
transceivers are members of the Texas
Instruments SCOPE

testability integrated-

circuit family. This family of devices supports IEEE
Standard 1149.1-1990 boundary scan to facilitate
testing of complex circuit-board assemblies. Scan
access to the test circuitry is accomplished via the
4-wire test access port (TAP) interface.

In the normal mode, these devices are functionally equivalent to the 'F245 and 'BCT245 octal bus transceivers.
The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device
terminals or to perform a self test on the boundary-test cells. Activating the TAP in normal mode does not affect
the functional operation of the SCOPE

octal bus transceivers.

In the test mode, the normal operation of the SCOPE

octal bus transceivers is inhibited and the test circuitry

is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform
boundary-scan test operations as described in IEEE Standard 1149.1-1990.

1996, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SCOPE is a trademark of Texas Instruments Incorporated.

SN54BCT8245A . . . JT PACKAGE

SN74BCT8245A . . . DW OR NT PACKAGE

(TOP VIEW)

SN54BCT8245A . . . FK PACKAGE

(TOP VIEW)

NC No internal connection

DIR

B1
B2
B3
B4

GND

B5
B6
B7
B8

TDO
TMS

OE
A1
A2
A3
A4
A5
V

A6
A7
A8
TDI
TCK

3 2 1 28 27

12 13

A8
TDI
TCK
NC
TMS
TDO
B8

A2
A1

OE
NC

DIR

B1
B2

14 15 16 17 18

GND

On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.

SN54BCT8245A, SN74BCT8245A
SCAN TEST DEVICES
WITH OCTAL BUS TRANSCEIVERS

SCBS043E MAY 1990 REVISED JULY 1996

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

description (continued)

Four dedicated test terminals control the operation of the test circuitry: test data input (TDI), test data output
(TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing
functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation
(PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.

The SN54BCT8245A is characterized for operation over the full military temperature range of 55

C to 125

The SN74BCT8245A is characterized for operation from 0

C to 70

FUNCTION TABLE

(normal mode)

INPUTS

OPERATION

DIR

OPERATION

B data to A bus

A data to B bus

Isolation

logic symbol

SCAN

'BCT8245A

TDI

TCK-IN

TMS

TCK

3 EN1 [BA]

DIR

TCK-OUT

3 EN2 [AB]

TDO

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DW, JT, and NT packages.

SN54BCT8245A, SN74BCT8245A
SCAN TEST DEVICES
WITH OCTAL BUS TRANSCEIVERS

SCBS043E MAY 1990 REVISED JULY 1996

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME

DESCRIPTION

A1A8

A-bus I/O ports. See function table for normal-mode logic. Internal pullups force these I/O ports to a high level if left
unconnected.

B1B8

B-bus I/O ports. See function table for normal-mode logic. Internal pullups force these I/O ports to a high level if left
unconnected.

DIR

Normal-function direction-control input. See function table for normal-mode logic. An internal pullup forces DIR to a high
level if left unconnected.

GND

Ground

Normal-function output-enable input. See function table for normal-mode logic. An internal pullup forces OE to a high level
if left unconnected.

TCK

Test clock. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the device are synchronous
to TCK. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK. An internal pullup forces
TCK to a high level if left unconnected.

TDI

Test data input. One of four terminals required by IEEE Standard 1149.1-1990. TDI is the serial input for shifting data through
the instruction register or selected data register. An internal pullup forces TDI to a high level if left unconnected.

TDO

Test data output. One of four terminals required by IEEE Standard 1149.1-1990. TDO is the serial output for shifting data
through the instruction register or selected data register. An internal pullup forces TDO to a high level when it is not active
and is not driven from an external source.

TMS

Test mode select. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the device through its TAP
controller states. An internal pullup forces TMS to a high level if left unconnected. TMS also provides the optional test reset
signal of IEEE Standard 1149.1-1990. This is implemented by recognizing a third logic level, double high (VIHH), at TMS.

VCC

Supply voltage

SN54BCT8245A, SN74BCT8245A

SCAN TEST DEVICES

WITH OCTAL BUS TRANSCEIVERS

SCBS043E MAY 1990 REVISED JULY 1996

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

test architecture

Serial-test information is conveyed by means of a 4-wire test bus, or TAP, that conforms to IEEE Standard
1149.1-1990. Test instructions, test data, and test control signals all are passed along this serial-test bus. The
TAP controller monitors two signals from the test bus, TCK and TMS. The TAP controller extracts the
synchronization (TCK) and state control (TMS) signals from the test bus and generates the appropriate on-chip
control signals for the test structures in the device. Figure 1 shows the TAP-controller state diagram.

The TAP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK, and
output data changes on the falling edge of TCK. This scheme ensures that data to be captured is valid for fully
one-half of the TCK cycle.

The functional block diagram shows the IEEE Standard 1149.1-1990 4-wire test bus and boundary-scan
architecture and the relationship among the test bus, the TAP controller, and the test registers. As shown, the
device contains an 8-bit instruction register and three test-data registers: an 18-bit boundary-scan register, a
2-bit boundary-control register, and a 1-bit bypass register.

Test-Logic-Reset

Run-Test/Idle

Select-DR-Scan

Capture-DR

Shift-DR

Exit1-DR

Pause-DR

Update-DR

TMS = L

TMS = H

TMS = L

TMS = H

TMS = L

TMS = H

TMS = L

TMS = H

TMS = L

Exit2-DR

Select-IR-Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Update-IR

TMS = L

TMS = H

TMS = L

TMS = H

TMS = L

TMS = H

TMS = L

Exit2-IR

TMS = L

TMS = H

TMS = L

TMS = H

TMS = L

TMS = H

TMS = L

Figure 1. TAP-Controller State Diagram

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