CY54FCT377T, CY74FCT377T
8-BIT REGISTERS
SCCS023A MAY 1994 REVISED OCTOBER 2001
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Function, Pinout, and Drive Compatible
With FCT and F Logic
D
Reduced V
OH
(Typically = 3.3 V) Versions of
Equivalent
FCT Functions
D
Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
D
I
off
Supports Partial-Power-Down Mode
Operation
D
Matched Rise and Fall Times
D
ESD Protection Exceeds JESD 22
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)
D
Fully Compatible With TTL Input and
Output Logic Levels
D
Clock Enable for Address and Data
Synchronization Application
D
Eight Edge-Triggered D-Type Flip-Flops
D
CY54FCT377T
32-mA Output Sink Current
12-mA Output Source Current
D
CY74FCT377T
64-mA Output Sink Current
32-mA Output Source Current
description
The 'FCT377T devices have eight triggered D-type flip-flops with individual data (D) inputs. The common
buffered clock (CP) inputs load all flip-flops simultaneously when the clock-enable (CE) input is low. The register
is fully edge triggered. The state of each D input at one setup time before the low-to-high clock transition is
transferred to the corresponding flip-flop output (O). CE must be stable only one setup time prior to the
low-to-high clock transition for predictable operation.
These devices are fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered down.
Copyright
2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN74FCT377T . . . Q OR SO PACKAGE
(TOP VIEW)
SN54FCT377T . . . L PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CE
O
0
D
0
D
1
O
1
O
2
D
2
D
3
O
3
GND
V
CC
O
7
D
7
D
6
O
6
O
5
D
5
D
4
O
4
CP
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
D
1
O
1
O
2
D
2
D
3
D
CE
3
GND
V
CC
D
7
D
6
O
6
O
5
D
5
O
CP
4
O
4
D
0
O
0
O
7
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
CY54FCT377T, CY74FCT377T
8-BIT REGISTERS
SCCS023A MAY 1994 REVISED OCTOBER 2001
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
ORDERING INFORMATION
TA
PACKAGE
SPEED
(ns)
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QSOP Q
Tape and reel
5.2
CY74FCT377CTQCT
FCT377C
SOIC
SO
Tube
5.2
CY74FCT377CTSOC
FCT377C
SOIC SO
Tape and reel
5.2
CY74FCT377CTSOCT
FCT377C
40
C to 85
C
QSOP Q
Tape and reel
7.2
CY74FCT377ATQCT
FCT377A
SOIC
SO
Tube
7.2
CY74FCT377ATSOC
FCT377A
SOIC SO
Tape and reel
7.2
CY74FCT377ATSOCT
FCT377A
QSOP Q
Tape and reel
13
CY74FCT377TQCT
FCT377
55
C to 125
C
LCC
L
Tube
5.5
CY54FCT377CTLMB
55
C to 125
C
LCC L
Tube
8.3
CY54FCT377ATLMB
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
OUTPUT
OPERATING
CP
CE
D
O
MODE
l
h
H
Load 1
l
l
L
Load 0
X
h
H
X
X
No change
Hold
H = High logic level, h = High logic level one setup time prior
to the low-to-high clock transition, L = Low logic level,
l = Low logic level one setup time prior to the low-to-high
clock transition, X = Don't care,
= Low-to-high clock
transition
logic diagram
CE
CP
D
CP
Q
To Seven Other Channels
D0
O0
1
11
3
2
CY54FCT377T, CY74FCT377T
8-BIT REGISTERS
SCCS023A MAY 1994 REVISED OCTOBER 2001
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range to ground potential
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC input voltage range
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC output voltage range
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC output current (maximum sink current/pin)
120 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 1): Q package
68
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SO package
58
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ambient temperature range with power applied, T
A
65
C to 135
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 2)
CY54FCT377T
CY74FCT377T
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
VCC
Supply voltage
4.5
5
5.5
4.75
5
5.25
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
IOH
High-level output current
12
32
mA
IOL
Low-level output current
32
64
mA
TA
Operating free-air temperature
55
125
40
85
C
NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation.
CY54FCT377T, CY74FCT377T
8-BIT REGISTERS
SCCS023A MAY 1994 REVISED OCTOBER 2001
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
CY54FCT377T
CY74FCT377T
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
VIK
VCC = 4.5 V,
IIN = 18 mA
0.7
1.2
V
VIK
VCC = 4.75 V,
IIN = 18 mA
0.7
1.2
V
VCC = 4.5 V,
IOH = 12 mA
2.4
3.3
VOH
VCC = 4 75 V
IOH = 32 mA
2
V
VCC = 4.75 V
IOH = 15 mA
2.4
3.3
VOL
VCC = 4.5 V,
IOL = 32 mA
0.3
0.55
V
VOL
VCC = 4.75 V,
IOL = 64 mA
0.3
0.55
V
Vhys
All inputs
0.2
0.2
V
II
VCC = 5.5 V,
VIN = VCC
5
A
II
VCC = 5.25 V,
VIN = VCC
5
A
IIH
VCC = 5.5 V,
VIN = 2.7 V
1
A
IIH
VCC = 5.25 V,
VIN = 2.7 V
1
A
IIL
VCC = 5.5 V,
VIN = 0.5 V
1
A
IIL
VCC = 5.25 V,
VIN = 0.5 V
1
A
I
VCC = 5.5 V,
VOUT = 0 V
60
120
225
mA
IOS
VCC = 5.25 V,
VOUT = 0 V
60
120
225
mA
Ioff
VCC = 0 V,
VOUT = 4.5 V
1
1
A
ICC
VCC = 5.5 V,
VIN
0.2 V,
VIN
VCC 0.2 V
0.1
0.2
mA
ICC
VCC = 5.25 V,
VIN
0.2 V,
VIN
VCC 0.2 V
0.1
0.2
mA
ICC
VCC = 5.5 V, VIN = 3.4 V, f1 = 0, Outputs open
0.5
2
mA
ICC
VCC = 5.25 V, VIN = 3.4 V, f1 = 0, Outputs open
0.5
2
mA
Typical values are at VCC = 5 V, TA = 25
C.
Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus
and/or sample-and-hold techniques are preferable to minimize internal chip heating and more accurately reflect operational values. Otherwise,
prolonged shorting of a high output can raise the chip temperature well above normal and cause invalid readings in other parametric tests. In
any sequence of parameter tests, IOS tests should be performed last.
Per TTL-driven input (VIN = 3.4 V); all other inputs at VCC or GND
CY54FCT377T, CY74FCT377T
8-BIT REGISTERS
SCCS023A MAY 1994 REVISED OCTOBER 2001
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
CY54FCT377T
CY74FCT377T
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
ICCD
VCC = 5.5 V, Outputs open,
One bit switching at 50% duty cycle, CE = GND,
VIN
0.2 V or VIN
VCC 0.2 V
0.06
0.12
mA/
ICCD
VCC = 5.25 V, Outputs open,
One bit switching at 50% duty cycle, CE = GND,
VIN
0.2 V or VIN
VCC 0.2 V
0.06
0.12
MHz
#
One bit
switching at
f1 = 5 MHz at
VIN
0.2 V or
VIN
VCC 0.2 V
0.7
1.4
#
VCC = 5.5 V,
Outputs open,
f1 = 5 MHz at
50% duty cycle
VIN = 3.4 V or GND
1.2
3.4
#
,
f0 = 10 MHz,
CE = GND
Eight bits
switching at
f1 = 2 5 MHz at
VIN
0.2 V or
VIN
VCC 0.2 V
1.6
3.2||
IC#
f1 = 2.5 MHz at
50% duty cycle
VIN = 3.4 V or GND
3.9
12.2||
mA
IC#
One bit
switching at
f1 = 5 MHz at
VIN
0.2 V or
VIN
VCC 0.2 V
0.7
1.4
mA
VCC = 5.25 V,
Outputs open,
f1 = 5 MHz at
50% duty cycle
VIN = 3.4 V or GND
1.2
3.4
,
f0 = 10 MHz,
CE = GND
Eight bits
switching at
f1 = 2 5 MHz at
VIN
0.2 V or
VIN
VCC 0.2 V
1.6
3.2||
f1 = 2.5 MHz at
50% duty cycle
VIN = 3.4 V or GND
3.9
12.2||
Ci
5
10
5
10
pF
Co
9
12
9
12
pF
Typical values are at VCC = 5 V, TA = 25
C.
This parameter is derived for use in total power-supply calculations.
# IC
= ICC +
ICC
DH
NT + ICCD (f0/2 + f1
N1)
Where:
IC
= Total supply current
ICC
= Power-supply current with CMOS input levels
ICC = Power-supply current for a TTL high input (VIN = 3.4 V)
DH
= Duty cycle for TTL inputs high
NT
= Number of TTL inputs at DH
ICCD = Dynamic current caused by an input transition pair (HLH or LHL)
f0
= Clock frequency for registered devices, otherwise zero
f1
= Input signal frequency
N1
= Number of inputs changing at f1
All currents are in milliamperes and all frequencies are in megahertz.
|| Values for these conditions are examples of the ICC formula.
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