SN54ABT827, SN74ABT827
10 BIT BUFFERS/DRIVERS
WITH 3 STATE OUTPUTS
SCBS159E - JANUARY 1991 - REVISED APRIL 2005
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
State-of-the-Art EPIC-
B
BiCMOS Design
Significantly Reduces Power Dissipation
D
Flow-Through Architecture Optimizes PCB
Layout
D
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D
Typical V
OLP
(Output Ground Bounce) < 1 V
at V
CC
= 5 V, T
A
= 25
C
D
High-Impedance State During Power Up
and Power Down
D
High-Drive Outputs (-32-mA I
OH
, 64-mA I
OL
)
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK), and
Plastic (NT) and Ceramic (JT) DIPs
description
These 10-bit buffers or bus drivers provide a
high-performance bus interface for wide data
paths or buses carrying parity.
The 3-state control gate is a 2-input AND gate with
active-low inputs so that, if either output-enable
(OE1 or OE2) input is high, all ten outputs are in
the high-impedance state. The 'ABT827 provides
true data at the outputs.
When V
CC
is between 0 and 2.1 V, the device
is in the high-impedance state during power up
or power down. However, to ensure
the high-impedance state above 2.1 V, OE should
be tied to V
CC
through a pullup resistor; the
minimum value of the resistor is determined by
the current-sinking capability of the driver.
The SN54ABT827 is characterized for operation over the full military temperature range of -55
C to 125
C. The
SN74ABT827 is characterized for operation from -40
C to 85
C.
FUNCTION TABLE
INPUTS
OUTPUT
OE1
OE2
A
OUTPUT
Y
L
L
L
L
L
L
H
H
H
X
X
Z
X
H
X
Z
SN54ABT827 . . . JT PACKAGE
SN74ABT827 . . . DB, DW, NT, OR PW PACKAGE
(TOP VIEW)
SN54ABT827 . . . FK PACKAGE
(TOP VIEW)
3 2 1 28 27
12 13
5
6
7
8
9
10
11
25
24
23
22
21
20
19
Y3
Y4
Y5
NC
Y6
Y7
Y8
A3
A4
A5
NC
A6
A7
A8
4
26
14 15 16 17 18
A9
A10
GND
NC
OE2
Y10
Y9
A2
A1
OE1
NC
Y1
Y2
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OE1
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
GND
V
CC
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
OE2
NC - No internal connection
Copyright
2005, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
EPIC-
B is a trademark of Texas Instruments.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54ABT827, SN74ABT827
10 BIT BUFFERS/DRIVERS
WITH 3 STATE OUTPUTS
SCBS159E - JANUARY 1991 - REVISED APRIL 2005
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic symbol
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for the DB, DW, JT, NT, and PW packages.
2
A1
3
A2
4
A3
5
A4
6
A5
Y1
23
Y2
22
Y3
21
Y4
20
Y5
19
Y6
18
Y7
17
Y8
16
7
A6
8
A7
9
A8
13
1
OE1
OE2
EN
&
Y9
15
Y10
14
10
A9
11
A10
1
logic diagram (positive logic)
Y1
To Nine Other Channels
OE1
OE2
A1
1
13
2
23
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
-0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
-0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or power-off state, V
O
-0.5 V to 5.5 V
. . . . . . . . . . . . . . . . . . .
Current into any output in the low state, I
O
: SN54ABT827 96
mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ABT827 128
mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
-18 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0)
-50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): DB package
104
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package
81
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NT package
67
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package
120
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
-65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages,
which use a trace length of zero.
SN54ABT827, SN74ABT827
10 BIT BUFFERS/DRIVERS
WITH 3 STATE OUTPUTS
SCBS159E - JANUARY 1991 - REVISED APRIL 2005
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
SN54ABT827
SN74ABT827
UNIT
MIN
MAX
MIN
MAX
UNIT
VCC
Supply voltage
4.5
5.5
4.5
5.5
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
VI
Input voltage
0
VCC
0
VCC
V
IOH
High-level output current
-24
-32
mA
IOL
Low-level output current
48
64
mA
t/
v
Input transition rise or fall rate
5
5
ns/V
t/
VCC
Power-up ramp rate
200
200
s/V
TA
Operating free-air temperature
-55
125
-40
85
C
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
SN54ABT827, SN74ABT827
10 BIT BUFFERS/DRIVERS
WITH 3 STATE OUTPUTS
SCBS159E - JANUARY 1991 - REVISED APRIL 2005
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25
C
SN54ABT827
SN74ABT827
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
VIK
VCC = 4.5 V,
II = -18 mA
-1.2
-1.2
-1.2
V
VCC = 4.5 V,
IOH = -3 mA
2.5
2.5
2.5
VOH
VCC = 5 V,
IOH = -3 mA
3
3
3
V
VOH
VCC = 4.5 V
IOH = -24 mA
2
2
V
VCC = 4.5 V
IOH = -32 mA
2*
2
VOL
VCC = 4.5 V
IOL = 48 mA
0.55
0.55
V
VOL
VCC = 4.5 V
IOL = 64 mA
0.55*
0.55
V
Vhys
100
mV
II
VCC = 0 to 5.5 V,
VI = VCC or GND
1
1
1
A
IOZPU
VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OE = X
50
10
50
A
IOZPD
VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OE = X
50
10
50
A
IOZH
VCC = 2.1 V to 5.5 V, VO = 2.7 V, OE
2 V
10
10
10
A
IOZL
VCC = 2.1 V to 5.5 V, VO = 0.5 V, OE
2 V
-10
-10
-10
A
Ioff
VCC = 0,
VI or VO
5.5 V
100
100
A
ICEX
VCC = 5.5 V, VO = 5.5 V
Outputs high
50
50
50
A
IO
VCC = 5.5 V,
VO = 2.5 V
-50
-140
-225
-50
-225
-50
-225
mA
VCC = 5.5 V, IO = 0,
Outputs high
80
250
250
250
A
ICC
VCC = 5.5 V, IO = 0,
VI = VCC or GND
Outputs low
35
40
40
40
mA
ICC
VI = VCC or GND
Outputs disabled
80
250
250
250
A
VCC = 5.5 V,
Outputs enabled
1.5
1.5
1.5
mA
ICC#
VCC = 5.5 V,
One input at 3.4 V,
Other inputs at V
or GND
Outputs disabled
50
50
50
A
ICC#
One input at 3.4 V,
Other inputs at VCC or GND Control inputs
1.5
1.5
1.5
mA
Ci
VI = 2.5 V or 0.5 V
4
pF
Co
VO = 2.5 V or 0.5 V
8
pF
* On products compliant to MIL-PRF-38535, this parameter does not apply.
All typical values are at VCC = 5 V.
This parameter is characterized, but not production tested.
This data sheet limit may vary among suppliers.
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
# This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
L
= 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
TA = 25
C
SN54ABT827
SN74ABT827
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
tPLH
A
Y
1.1
2.6
4.4
1.1
4.9
1.1
4.8
ns
tPHL
A
Y
1.1
2.3
4.1
1.1
4.8
1.1
4.7
ns
tPZH
OE
Y
1
3.2
5.1
1
6
1
5.9
ns
tPZL
OE
Y
1
3.3
5.9
1
7.1
1
6.9
ns
tPHZ
OE
Y
2
4.9
6.3
2
7
2
6.8
ns
tPLZ
OE
Y
1.3
4.2
6.6
1.3
7.9
1.3
6.9
ns
This data sheet limit may vary among suppliers.
SN54ABT827, SN74ABT827
10 BIT BUFFERS/DRIVERS
WITH 3 STATE OUTPUTS
SCBS159E - JANUARY 1991 - REVISED APRIL 2005
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
1.5 V
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
7 V
Open
GND
500
500
Data Input
Timing Input
1.5 V
3 V
0 V
1.5 V
1.5 V
3 V
0 V
3 V
0 V
1.5 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
1.5 V
1.5 V
3 V
0 V
1.5 V
1.5 V
Input
1.5 V
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V
1.5 V
3.5 V
0 V
1.5 V
VOL + 0.3 V
1.5 V
VOH - 0.3 V
0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7 V
Open
TEST
S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr
2.5 ns, tf
2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
1.5 V
Figure 1. Load Circuit and Voltage Waveforms
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