SN54ABT8646, SN74ABT8646

SCAN TEST DEVICES WITH

OCTAL BUS TRANSCEIVERS AND REGISTERS

SCBS123F - AUGUST 1992 - REVISED APRIL 2004

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Members of the Texas Instruments
SCOPE

Family of Testability Products

Compatible With the IEEE Standard
1149.1-1990 (JTAG) Test Access Port and
Boundary-Scan Architecture

Functionally Equivalent to 'F646 and
'ABT646 in the Normal-Function Mode

SCOPE

Instruction Set

- IEEE Standard 1149.1-1990 Required

Instructions, Optional INTEST, CLAMP,
and HIGHZ

- Parallel-Signature Analysis at Inputs

With Masking Option

- Pseudorandom Pattern Generation From

Outputs

- Sample Inputs/Toggle Outputs
- Binary Count From Outputs
- Even-Parity Opcodes

Two Boundary-Scan Cells Per I/O for
Greater Flexibility

State-of-the-Art EPIC-

BiCMOS Design

Significantly Reduces Power Dissipation

Package Options Include Plastic
Small-Outline (DW) and Shrink
Small-Outline (DL) Packages, Ceramic Chip
Carriers (FK), and Standard Ceramic DIPs
(JT)

description

The 'ABT8646 and scan-test devices with octal
bus transceivers and registers are members of the
Texas Instruments SCOPE

testability

integrated-circuit family. This family of devices
supports IEEE Standard 1149.1-1990 boundary
scan to facilitate testing of complex circuit-board
assemblies. Scan access to the test circuitry is
accomplished via the 4-wire test access port
(TAP) interface.

In the normal mode, these devices are functionally equivalent to the 'F646 and 'ABT646 octal bus transceivers
and registers. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing
at the device pins or to perform a self-test on the boundary-test cells. Activating the TAP in normal mode does
not affect the functional operation of the SCOPE

octal bus transceivers and registers.

2004, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SCOPE and EPIC-

B are trademarks of Texas Instruments.

CLKAB

SAB

DIR

A1
A2
A3

GND

A4
A5
A6
A7
A8

TDO
TMS

CLKBA
SBA
OE
B1
B2
B3
B4
V

B5
B6
B7
B8
TDI
TCK

3 2 1

13 14

B7
B8
TDI
TCK
TMS
TDO
A8

SBA

CLKBA
CLKAB

SAB

DIR

15 16 17 18

28 27 26

SN54ABT8646 . . . JT PACKAGE

SN74ABT8646 . . . DL OR DW PACKAGE

(TOP VIEW)

SN54ABT8646 . . . FK PACKAGE

(TOP VIEW)

On products compliant to MIL PRF 38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

SN54ABT8646, SN74ABT8646

SCAN TEST DEVICES WITH

OCTAL BUS TRANSCEIVERS AND REGISTERS

SCBS123F - AUGUST 1992 - REVISED APRIL 2004

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

description (continued)

Transceiver function is controlled by output-enable (OE) and direction (DIR) inputs. When OE is low, the
transceiver is active and operates in the A-to-B direction when DIR is high or in the B-to-A direction when DIR
is low. When OE is high, both the A and B outputs are in the high-impedance state, effectively isolating both
buses.

Data flow is controlled by clock (CLKAB and CLKBA) and select (SAB and SBA) inputs. Data on the A bus is
clocked into the associated registers on the low-to-high transition of CLKAB. When SAB is low, real-time A data
is selected for presentation to the B bus (transparent mode). When SAB is high, stored A data is selected for
presentation to the B bus (registered mode). The function of the CLKBA and SBA inputs mirrors that of CLKAB
and SAB, respectively. Figure 1 shows the four fundamental bus-management functions that can be performed
with the 'ABT8646.

In the test mode, the normal operation of the SCOPE

bus transceivers and registers is inhibited, and the test

circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry
performs boundary-scan test operations as described in IEEE Standard 1149.1-1990.

Four dedicated test pins control the operation of the test circuitry: test data input (TDI), test data output (TDO),
test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions
such as parallel-signature analysis (PSA) on data inputs and pseudorandom pattern generation (PRPG) from
data outputs. All testing and scan operations are synchronized to the TAP interface.

The SN54ABT8646 is characterized for operation over the full military temperature range of -55

C to 125

The SN74ABT8646 is characterized for operation from -40

C to 85

FUNCTION TABLE

INPUTS

DATA I/O

OPERATION OR FUNCTION

DIR

CLKAB

CLKBA

SAB

SBA

A1-A8

B1-B8

OPERATION OR FUNCTION

Input

Unspecified

Store A, B unspecified

Unspecified

Input

Store B, A unspecified

Input

Store A and B data

H or L

Input disabled

Isolation, hold storage

Output

Input

Real-time B data to A bus

H or L

Output

Input disabled

Stored B data to A bus

Input

Output

Real-time A data to B bus

H or L

Input disabled

Output

Stored A data to B bus

The data-output functions can be enabled or disabled by various signals at OE and DIR. Data-input functions are always enabled; i.e., data at

the bus pins is stored on every low-to-high transition of the clock inputs.

SN54ABT8646, SN74ABT8646

SCAN TEST DEVICES WITH

OCTAL BUS TRANSCEIVERS AND REGISTERS

SCBS123F - AUGUST 1992 - REVISED APRIL 2004

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

DIR

CLKAB

CLKBA

SAB

SBA

REAL-TIME TRANSFER

BUS B TO BUS A

DIR

CLKAB

CLKBA

SAB

SBA

REAL-TIME TRANSFER

BUS A TO BUS B

DIR

CLKAB

CLKBA

SAB

SBA

STORAGE FROM

A, B, OR A AND B

DIR

CLKAB

CLKBA

H or L

SAB

SBA

TRANSFER STORED DATA

TO A AND/OR B

H or L

BUS B

BUS A

BUS B

BUS A

BUS B

BUS A

BUS B

BUS A

Pin numbers shown are for the DL, DW, and JT packages.

Figure 1. Bus-Management Functions

SN54ABT8646, SN74ABT8646

SCAN TEST DEVICES WITH

OCTAL BUS TRANSCEIVERS AND REGISTERS

SCBS123F - AUGUST 1992 - REVISED APRIL 2004

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME

DESCRIPTION

A1-A8

Normal-function A-bus I/O ports. See function table for normal-mode logic.

B1-B8

Normal-function B-bus I/O ports. See function table for normal-mode logic.

CLKAB, CLKBA

Normal-function clock inputs. See function table for normal-mode logic.

DIR

Normal-function direction-control input. See function table for normal-mode logic.

GND

Ground

Normal-function output-enable input. See function table for normal-mode logic.

SAB, SBA

Normal-function select inputs. See function table for normal-mode logic.

TCK

Test clock. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the device are synchronous
to TCK. Data is captured on the rising edge of TCK, and outputs change on the falling edge of TCK.

TDI

Test data input. One of four terminals required by IEEE Standard 1149.1-1990. TDI is the serial input for shifting data
through the instruction register or selected data register. An internal pullup forces TDI to a high level if left unconnected.

TDO

Test data output. One of four terminals required by IEEE Standard 1149.1-1990. TDO is the serial output for shifting data
through the instruction register or selected data register.

TMS

Test mode select. One of four terminals required by IEEE Standard 1149.1-1990. TMS input directs the device through
its TAP controller states. An internal pullup forces TMS to a high level if left unconnected.

VCC

Supply voltage

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