SN54ABT18646

SCAN TEST DEVICE WITH

18-BIT TRANSCEIVERS AND REGISTERS

SGBS306 AUGUST 1992 REVISED AUGUST 1994

1994, Texas Instruments Incorporated

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Members of the Texas Instruments
SCOPE

Family of Testability Products

Members of the Texas Instruments
Widebus

Family

Compatible With the IEEE Standard
1149.1-1990 (JTAG) Test Access Port and
Boundary-Scan Architecture

Includes D-Type Flip-Flops and Control
Circuitry to Provide Multiplexed
Transmission of Stored and Real-Time Data

Two Boundary-Scan Cells per I/O for
Greater Flexibility

State-of-the-Art

EPIC-

BiCMOS Design

Significantly Reduces Power Dissipation

SCOPE

Instruction Set

 IEEE Standard 1149.1-1990 Required

Instructions, Optional INTEST, CLAMP
and HIGHZ

 Parallel-Signature Analysis at Inputs With

Masking Option

 Pseudo-Random Pattern Generation

From Outputs

Sample Inputs/Toggle Outputs
Binary Count From Outputs
Device Identification
Even-Parity Opcodes

Packaged in 68-Pin Ceramic Quad Flat
Package

1B4
1B5
1B6
GND
1B7
1B8
1B9
V

NC
2B1
2B2
2B3
2B4
GND
2B5
2B6
2B7

1A3
1A4
1A5

GND

1A6
1A7
1A8
1A9

2A1
2A2
2A3

GND

2A4
2A5
2A6

TMS

1CLKBA

1A2

1A1

1OE

GND

1SAB

1CLKAB

TDO

TCK

2CLKBA

2SBA

2A9

GND

2OE

2SAB

2CLKAB

TDI

2A7

2A8

1SBA

1DIR

GND

2DIR

2B9

2B8

GND

1B1

1B2

1B3

28 29

31 32 33 34

8 7

1 68 67

35 36 37 38 39

66 65

64 63 62 61

40 41 42 43

HV PACKAGE

(TOP VIEW)

NC No internal connection

SCOPE, Widebus, and EPIC-

B are trademarks of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

SN54ABT18646
SCAN TEST DEVICE WITH
18-BIT TRANSCEIVERS AND REGISTERS

SGBS306 AUGUST 1992 REVISED AUGUST 1994

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

description

The SN54ABT18646 scan test device with 18-bit bus transceivers and registers is a member of the Texas
Instruments SCOPE

testability integrated circuit family. This family of devices supports IEEE Standard

1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test
circuitry is accomplished via the 4-wire test access port (TAP) interface.

In the normal mode, the SN54ABT18646 is an 18-bit bus transceiver and register that allows for multiplexed
transmission of data directly from the input bus or from the internal registers. It can be used either as two 9-bit
transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples
of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP
in the normal mode does not affect the functional operation of the SCOPE

bus transceivers and registers.

Transceiver function is controlled by output-enable (OE) and direction (DIR) inputs. When OE is low, the
transceiver is active and operates in the A-to-B direction when DIR is high or in the B-to-A direction when DIR
is low. When OE is high, both the A and B outputs are in the high-impedance state, effectively isolating both
buses.

Data flow is controlled by clock (CLKAB and CLKBA) and select (SAB and SBA) inputs. Data on the A bus is
clocked into the associated registers on the low-to-high transition of CLKAB. When SAB is low, real-time A data
is selected for presentation to the B bus (transparent mode). When SAB is high, stored A data is selected for
presentation to the B bus (registered mode). The function of the CLKBA and SBA inputs mirrors that of CLKAB
and SAB, respectively. Figure 1 illustrates the four fundamental bus-management functions that can be
performed with the

SN54

ABT18646.

In the test mode, the normal operation of the SCOPE

bus transceivers and registers is inhibited, and the test

circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry can
perform boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990.

Four dedicated test pins observe and control the operation of the test circuitry: test data input (TDI), test data
output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing
functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation
(PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.

Additional flexibility is provided in the test mode through the use of two boundary scan cells (BSCs) for each
I/O pin. This allows independent test data to be captured and forced at either bus (A or B). A PSA/COUNT
instruction also is included to ease the testing of memories and other circuits where a binary count addressing
scheme is useful.

The SN54ABT18646 is characterized over the full military temperature range of 55

C to 125

FUNCTION TABLE

(normal mode, each 9-bit section)

INPUTS

DATA I/O

OPERATION OR FUNCTION

DIR

CLKAB

CLKBA

SAB

SBA

A1 THRU A9

B1 THRU B9

OPERATION OR FUNCTION

Input

Unspecified

Store A, B unspecified

Unspecified

Input

Store B, A unspecified

Input

Store A and B data

Input disabled

Isolation, hold storage

Output

Input

Real-time B data to A bus

Output

Input disabled

Stored B data to A bus

Input

Output

Real-time A data to B bus

Input disabled

Output

Stored A data to B bus

The data output functions can be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled; i.e.,

data at the bus pins is stored on every low-to-high transition of the clock inputs.

SN54ABT18646

SCAN TEST DEVICE WITH

18-BIT TRANSCEIVERS AND REGISTERS

SGBS306 AUGUST 1992 REVISED AUGUST 1994

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Terminal Functions

TERMINAL NAME

DESCRIPTION

1A11A9,

2A1 2A9

Normal-function A-bus I/O ports. See function table for normal-mode logic.

1B11B9,

2B1 2B9

Normal-function B-bus I/O ports. See function table for normal-mode logic.

1CLKAB, 1CLKBA,

2CLKAB, 2CLKBA

Normal-function clock inputs. See function table for normal-mode logic.

1DIR, 2DIR

Normal-function direction controls. See function table for normal-mode logic.

GND

Ground

1OE, 2OE

Normal-function output enables. See function table for normal-mode logic.

1SAB, 1SBA,

2SAB, 2SBA

Normal-function select controls. See function table for normal-mode logic.

TCK

Test clock. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the device are synchronous
to TCK. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK.

TDI

Test data input. One of four terminals required by IEEE Standard 1149.1-1990. TDI is the serial input for shifting data
through the instruction register or selected data register. An internal pullup forces TDI to a high level if left unconnected.

TDO

Test data output. One of four terminals required by IEEE Standard 1149.1-1990. TDO is the serial output for shifting data
through the instruction register or selected data register.

TMS

Test mode select. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the device through its TAP
controller states. An internal pullup forces TMS to a high level if left unconnected.

VCC

Supply voltage

SN54ABT18646
SCAN TEST DEVICE WITH
18-BIT TRANSCEIVERS AND REGISTERS

SGBS306 AUGUST 1992 REVISED AUGUST 1994

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

test architecture

Serial-test information is conveyed by means of a 4-wire test bus or TAP that conforms to IEEE Standard
1149.1-1990. Test instructions, test data, and test control signals all are passed along this serial-test bus. The
TAP controller monitors two signals from the test bus, namely TCK and TMS. The TAP controller extracts the
synchronization (TCK) and state control (TMS) signals from the test bus and generate the appropriate on-chip
control signals for the test structures in the device. Figure 2 shows the TAP-controller state diagram.

The TAP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK, and
output data changes on the falling edge of TCK. This scheme ensures that data to be captured is valid for fully
one-half of the TCK cycle.

The functional block diagram illustrates the IEEE Standard 1149.1-1990 4-wire test bus and boundary-scan
architecture and the relationship among the test bus, the TAP controller, and the test registers. As illustrated,
the device contains an 8-bit instruction register and four test data registers: an 88-bit boundary-scan register,
a 21-bit boundary-control register, a 1-bit bypass register, and a 32-bit device-identification register.

Test-Logic-Reset

Run-Test/Idle

Select-DR-Scan

Capture-DR

Shift-DR

Exit1-DR

Pause-DR

Update-DR

TMS = L

TMS = H

TMS = L

TMS = H

TMS = L

TMS = H

TMS = L

TMS = H

TMS = L

Exit2-DR

Select-IR-Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Update-IR

TMS = L

TMS = H

TMS = L

TMS = H

TMS = L

TMS = H

TMS = L

Exit2-IR

TMS = L

TMS = H

TMS = L

TMS = H

TMS = L

TMS = H

TMS = L

Figure 2. TAP-Controller State Diagram

SN54ABT18646

SCAN TEST DEVICE WITH

18-BIT TRANSCEIVERS AND REGISTERS

SGBS306 AUGUST 1992 REVISED AUGUST 1994

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

state diagram description

The TAP controller is a synchronous finite state machine that provides test control signals throughout the device.
The state diagram is illustrated in Figure 2 and is in accordance with IEEE Standard 1149.1-1990. The TAP
controller proceeds through its states based on the level of TMS at the rising edge of TCK.

As illustrated, the TAP controller consists of 16 states. There are six stable states (indicated by a looping arrow
in the state diagram) and ten unstable states. A stable state is defined as a state the TAP controller can retain
for consecutive TCK cycles. Any state that does not meet this criterion is an unstable state.

There are two main paths through the state diagram: one to access and control the selected data register and
one to access and control the instruction register. Only one register can be accessed at a time.

Test-Logic-Reset

The device powers up in the Test-Logic-Reset state. In the stable Test-Logic-Reset state, the test logic is reset
and is disabled so that the normal logic function of the device is performed. The instruction register is reset to
an opcode that selects the optional IDCODE instruction, if supported, or the BYPASS instruction. Certain data
registers also can be reset to their power-up values.

The state machine is constructed such that the TAP controller returns to the Test-Logic-Reset state in no more
than five TCK cycles if TMS is left high. The TMS pin has an internal pullup resistor that forces it high if left
unconnected or if a board defect causes it to be open circuited.

For the SN54ABT18646, the instruction register is reset to the binary value 10000001, which selects the
IDCODE instruction. Bits 87 84 in the boundary-scan register are reset to logic 0, ensuring that these cells,
which control A-port and B-port outputs, are set to benign values (i.e., if test mode were invoked, the outputs
would be at high impedance state). Reset values of other bits in the boundary-scan register should be
considered indeterminate. The boundary-control register is reset to the binary value 000000000000000000010,
which selects the PSA test operation with no input masking.

Run-Test/Idle

The TAP controller must pass through the Run-Test/Idle state (from Test-Logic-Reset) before executing any test
operations. The Run-Test/Idle state also can be entered following data-register or instruction-register scans.
Run-Test/Idle is a stable state in which the test logic can be actively running a test or can be idle.

The test operations selected by the boundary-control register are performed while the TAP controller is in the
Run-Test/Idle state.

Select-DR-Scan, Select-lR-Scan

No specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the TAP controller exits
either of these states on the next TCK cycle. These states allow the selection of either data-register scan or
instruction-register scan.

Capture-DR

When a data-register scan is selected, the TAP controller must pass through the Capture-DR state. In the
Capture-DR state, the selected data register can capture a data value as specified by the current instruction.
Such capture operations occur on the rising edge of TCK upon which the TAP controller exits the Capture-DR
state.

Shift-DR

Upon entry to the Shift-DR state, the data register is placed in the scan path between TDI and TDO and, on the
first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic
level present in the least significant bit of the selected data register.

SN54ABT18646
SCAN TEST DEVICE WITH
18-BIT TRANSCEIVERS AND REGISTERS

SGBS306 AUGUST 1992 REVISED AUGUST 1994

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Shift-DR (continued)

While in the stable Shift-DR state, data is serially shifted through the selected data register on each TCK cycle.
The first shift occurs on the first rising edge of TCK after entry to the Shift-DR state (i.e., no shifting occurs during
the TCK cycle in which the TAP controller changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR).
The last shift occurs on the rising edge of TCK upon which the TAP controller exits the Shift-DR state.

Exit1-DR, Exit2-DR

The Exit1-DR and Exit2-DR states are temporary states that end a data-register scan. It is possible to return
to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register. On the first falling
edge of TCK after entry to Exit1-DR, TDO goes from the active state to the high-impedance state.

Pause-DR

No specific function is performed in the stable Pause-DR state, in which the TAP controller can remain
indefinitely. The Pause-DR state can suspend and resume data-register scan operations without loss of data.

Update-DR

If the current instruction calls for the selected data register to be updated with current data, such update occurs
on the falling edge of TCK following entry to the Update-DR state.

Capture-IR

When an instruction-register scan is selected, the TAP controller must pass through the Capture-IR state. In the
Capture-IR state, the instruction register captures its current status value. This capture operation occurs on the
rising edge of TCK upon which the TAP controller exits the Capture-IR state. For the SN54ABT18646, the status
value loaded in the Capture-IR state is the fixed binary value 10000001.

Shift-IR

Upon entry to the Shift-IR state, the instruction register is placed in the scan path between TDI and TDO and,
on the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to
the logic level present in the least significant bit of the instruction register.

While in the stable Shift-IR state, instruction data is serially shifted through the instruction register on each TCK
cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-IR state (i.e., no shifting occurs
during the TCK cycle in which the TAP controller changes from Capture-IR to Shift-IR or from Exit2-IR to
Shift-IR). The last shift occurs on the rising edge of TCK upon which the TAP controller exits the Shift-IR state.

Exit1-IR, Exit2-IR

The Exit1-IR and Exit2-IR states are temporary states that end an instruction-register scan. It is possible to
return to the Shift-IR state from either Exit1-IR or Exit2-IR without recapturing the instruction register. On the
first falling edge of TCK after entry to Exit1-IR, TDO goes from the active state to the high-impedance state.

Pause-IR

No specific function is performed in the stable Pause-IR state, in which the TAP controller can remain indefinitely.
The Pause-IR state can suspend and resume instruction-register scan operations without loss of data.

Update-IR

The current instruction is updated and takes effect on the falling edge of TCK following entry to the Update-IR
state.

SN54ABT18646

SCAN TEST DEVICE WITH

18-BIT TRANSCEIVERS AND REGISTERS

SGBS306 AUGUST 1992 REVISED AUGUST 1994

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

register overview

With the exception of the bypass and device-identification registers, any test register can be thought of as a
serial-shift register with a shadow latch on each bit. The bypass and device-identification registers differ in that
they contain only a shift register. During the appropriate capture state (Capture-IR for instruction register,
Capture-DR for data registers), the shift register can be parallel loaded from a source specified by the current
instruction. During the appropriate shift state (Shift-IR or Shift-DR), the contents of the shift register are shifted
out from TDO while new contents are shifted in at TDI. During the appropriate update state (Update-IR or
Update-DR), the shadow latches are updated from the shift register.

instruction register description

The instruction register (IR) is eight bits long and tells the device what instruction is to be executed. Information
contained in the instruction includes the mode of operation (either normal mode, in which the device performs
its normal logic function, or test mode, in which the normal logic function is inhibited or altered), the test operation
to be performed, which of the four data registers is to be selected for inclusion in the scan path during
data-register scans, and the source of data to be captured into the selected data register during Capture-DR.

Table 4 lists the instructions supported by the SN54ABT18646. The even-parity feature specified for SCOPE

devices is supported in this device. Bit 7 of the instruction opcode is the parity bit. Any instructions that are
defined for SCOPE

devices but are not supported by this device default to BYPASS.

During Capture-IR, the IR captures the binary value 10000001. As an instruction is shifted in, this value will be
shifted out via TDO and can be inspected as verification that the IR is in the scan path. During Update-IR, the
value that has been shifted into the IR is loaded into shadow latches. At this time, the current instruction is
updated and any specified mode change takes effect. At power up or in the Test-Logic-Reset state, the IR is
reset to the binary value 10000001, which selects the IDCODE instruction. The IR order of scan is illustrated
in Figure 3.

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

TDO

TDI

Bit 7

Parity

(MSB)

Bit 0

(LSB)

Figure 3. Instruction Register Order of Scan

SN54ABT18646
SCAN TEST DEVICE WITH
18-BIT TRANSCEIVERS AND REGISTERS

SGBS306 AUGUST 1992 REVISED AUGUST 1994

410

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

data register description

boundary-scan register

The boundary-scan register (BSR) is 88 bits long. It contains one boundary-scan cell (BSC) for each
normal-function input pin and two BSCs for each normal-function I/O pin (one for input data and one for output
data). The BSR is used 1) to store test data that is to be applied internally to the inputs of the normal on-chip
logic and/or externally to the device output pins, and/or 2) to capture data that appears internally at the outputs
of the normal on-chip logic and/or externally at the device input pins.

The source of data to be captured into the BSR during Capture-DR is determined by the current instruction. The
contents of the BSR can change during Run-Test/Idle as determined by the current instruction. At power up or
in Test-Logic-Reset, BSCs 8784 are reset to logic 0, ensuring that these cells, which control A-port and B-port
outputs are set to benign values (i.e., if test mode were invoked, the outputs would be at high impedance state).
Reset values of other BSCs should be considered indeterminate.

The BSR order of scan is from TDI through bits 87 0 to TDO. Table 1 shows the BSR bits and their associated
device pin signals.

Table 1. Boundary-Scan-Register Configuration

BSR BIT

NUMBER

DEVICE

SIGNAL

BSR BIT

NUMBER

DEVICE

SIGNAL

BSR BIT

NUMBER

DEVICE

SIGNAL

BSR BIT

NUMBER

DEVICE

SIGNAL

BSR BIT

NUMBER

DEVICE

SIGNAL

2OEB

2A9-I

2A9-O

2B9-I

2B9-O

1OEB

2A8-I

2A8-O

2B8-I

2B8-O

2OEA

2A7-I

2A7-O

2B7-I

2B7-O

1OEA

2A6-I

2A6-O

2B6-I

2B6-O

2DIR

2A5-I

2A5-O

2B5-I

2B5-O

1DIR

2A4-I

2A4-O

2B4-I

2B4-O

2OE

2A3-I

2A3-O

2B3-I

2B3-O

1OE

2A2-I

2A2-O

2B2-I

2B2-O

2CLKAB

2A1-I

2A1-O

2B1-I

2B1-O

1CLKAB

1A9-I

1A9-O

1B9-I

1B9-O

2CLKBA

1A8-I

1A8-O

1B8-I

1B8-O

1CLKBA

1A7-I

1A7-O

1B7-I

1B7-O

2SAB

1A6-I

1A6-O

1B6-I

1B6-O

1SAB

1A5-I

1A5-O

1B5-I

1B5-O

2SBA

1A4-I

1A4-O

1B4-I

1B4-O

1SBA

1A3-I

1A3-O

1B3-I

1B3-O

1A2-I

1A2-O

1B2-I

1B2-O

1A1-I

1A1-O

1B1-I

1B1-O

boundary-control register

The boundary-control register (BCR) is 21 bits long. The BCR is used in the context of the RUNT instruction to
implement additional test operations not included in the basic SCOPE

instruction set. Such operations include

PRPG, PSA with input masking, and binary count up (COUNT). Table 5 shows the test operations that are
decoded by the BCR.

During Capture-DR, the contents of the BCR are not changed. At power up or in Test-Logic-Reset, the BCR is
reset to the binary value 000000000000000000010, which selects the PSA test operation with no input masking.

The BCR order of scan is from TDI through bits 20 0 to TDO. Table 2 shows the BCR bits and their associated
test control signals.

SN54ABT18646

SCAN TEST DEVICE WITH

18-BIT TRANSCEIVERS AND REGISTERS

SGBS306 AUGUST 1992 REVISED AUGUST 1994

411

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Table 2. Boundary-Control-Register Configuration

BCR BIT

NUMBER

TEST

CONTROL

SIGNAL

BCR BIT

NUMBER

TEST

CONTROL

SIGNAL

BCR BIT

NUMBER

TEST

CONTROL

SIGNAL

MASK2.9

MASK1.9

OPCODE2

MASK2.8

MASK1.8

OPCODE1

MASK2.7

MASK1.7

OPCODE0

MASK2.6

MASK1.6

MASK2.5

MASK1.5

MASK2.4

MASK1.4

MASK2.3

MASK1.3

MASK2.2

MASK1.2

MASK2.1

MASK1.1

bypass register

The bypass register is a 1-bit scan path that can be selected to shorten the length of the system scan path,
thereby reducing the number of bits per test pattern that must be applied to complete a test operation. During
Capture-DR, the bypass register captures a logic 0. The bypass register order of scan is illustrated in
Figure 4.

Bit 0

TDO

TDI

Figure 4. Bypass Register Order of Scan

device-identification register

The device-identification register (IDR) is 32 bits long. It can be selected and read to identify the manufacturer,
part number, and version of this device.

During Capture-DR, the binary value 00000000000000001000000000101111 (0000802F, hex) is captured in
the IDR to identify this device as Texas Instruments SN54ABT18646.

The device identification register order of scan is from TDI through bits 31 0 to TDO. Table 3 shows the IDR
bits and their significance.

SN54ABT18646
SCAN TEST DEVICE WITH
18-BIT TRANSCEIVERS AND REGISTERS

SGBS306 AUGUST 1992 REVISED AUGUST 1994

412

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Table 3. Device-Identification-Register Configuration

IDR BIT

NUMBER

IDENTIFICATION

SIGNIFICANCE

IDR BIT

NUMBER

IDENTIFICATION

SIGNIFICANCE

IDR BIT

NUMBER

IDENTIFICATION

SIGNIFICANCE

VERSION3

PARTNUMBER15

MANUFACTURER10

VERSION2

PARTNUMBER14

MANUFACTURER09

VERSION1

PARTNUMBER13

MANUFACTURER08

VERSION0

PARTNUMBER12

MANUFACTURER07

PARTNUMBER11

MANUFACTURER06

PARTNUMBER10

MANUFACTURER05

PARTNUMBER09

MANUFACTURER04

PARTNUMBER08

MANUFACTURER03

PARTNUMBER07

MANUFACTURER02

PARTNUMBER06

MANUFACTURER01

PARTNUMBER05

MANUFACTURER00

PARTNUMBER04

LOGIC1

PARTNUMBER03

PARTNUMBER02

PARTNUMBER01

PARTNUMBER00

Note that for TI products, bits 11 0 of the device identification register always contain the binary value 000000101111

(02F, hex).

instruction-register opcode description

The instruction-register opcodes are shown in Table 4. The following descriptions detail the operation of each
instruction.

Table 4. Instruction-Register Opcodes

BINARY CODE

BIT 7

BIT 0

MSB

LSB

SCOPE OPCODE

DESCRIPTION

SELECTED DATA

REGISTER

MODE

00000000

EXTEST

Boundary scan

Test

10000001

IDCODE

Identification read

Device identification

Normal

10000010

SAMPLE/PRELOAD

Sample boundary

Boundary scan

Normal

00000011

INTEST

Boundary scan

Test

10000100

BYPASS

Bypass scan

Bypass

Normal

00000101

BYPASS

Bypass scan

Bypass

Normal

00000110

HIGHZ

Control boundary to high impedance

Bypass

Modified test

10000111

CLAMP

Control boundary to 1/0

Bypass

Test

10001000

BYPASS

Bypass scan

Bypass

Normal

00001001

RUNT

Boundary run test

Bypass

Test

00001010

READBN

Boundary read

Boundary scan

Normal

10001011

READBT

Boundary read

Boundary scan

Test

00001100

CELLTST

Boundary self test

Boundary scan

Normal

10001101

TOPHIP

Boundary toggle outputs

Bypass

Test

10001110

SCANCN

Boundary-control register scan

Boundary control

Normal

00001111

SCANCT

Boundary-control register scan

Boundary control

Test

All others

BYPASS

Bypass scan

Bypass

Normal

Bit 7 is used to maintain even parity in the 8-bit instruction.
The BYPASS instruction is executed in lieu of a SCOPE

instruction that is not supported in the SN54ABT18646.

SN54ABT18646

SCAN TEST DEVICE WITH

18-BIT TRANSCEIVERS AND REGISTERS

SGBS306 AUGUST 1992 REVISED AUGUST 1994

413

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

boundary scan

This instruction conforms to the IEEE Standard 1149.1-1990 EXTEST and INTEST instructions. The BSR is
selected in the scan path. Data appearing at the device input pins is captured in the input BSCs, while data
appearing at the outputs of the normal on-chip logic is captured in the output BSCs. Data scanned into the input
BSCs is applied to the inputs of the normal on-chip logic, while data scanned into the output BSCs is applied
to the device output pins. The device operates in the test mode.

bypass scan

This instruction conforms to the IEEE Standard 1149.1-1990 BYPASS instruction. The bypass register is
selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device
operates in the normal mode.

sample boundary

This instruction conforms to the IEEE Standard 1149.1-1990 SAMPLE/PRELOAD instruction. The BSR is
selected in the scan path. Data appearing at the device input pins is captured in the input BSCs, while data
appearing at the outputs of the normal on-chip logic is captured in the output BSCs. The device operates in the
normal mode.

control boundary to high impedance

This instruction conforms to the IEEE Standard 1149.1a-1993 instruction. The bypass register is selected in the
scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device operates in a
modified test mode in which all device I/O pins are placed in the high-impedance state, the device input pins
remain operational, and the normal on-chip logic function is performed.

control boundary to 1/0

This instruction conforms to the IEEE Standard 1149.1a-1993 instruction. The bypass register is selected in the
scan path. A logic 0 value is captured in the bypass register during Capture-DR. Data in the input BSCs is applied
to the inputs of the normal on-chip logic, while data in the output BSCs is applied to the device output pins. The
device operates in the test mode.

boundary-run test

The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during
Capture-DR. The device operates in the test mode. The test operation specified in the BCR is executed during
Run-Test/Idle. The five test operations decoded by the BCR are: sample inputs/toggle outputs (TOPSIP),
PRPG, PSA, simultaneous PSA and PRPG (PSA/PRPG), and simultaneous PSA and binary count up
(PSA/COUNT).

boundary read

The BSR is selected in the scan path. The value in the BSR remains unchanged during Capture-DR. This
instruction is useful for inspecting data after a PSA operation.

boundary self test

The BSR is selected in the scan path. All BSCs capture the inverse of their current values during Capture-DR.
In this way, the contents of the shadow latches can be read out to verify the integrity of both shift-register and
shadow-latch elements of the BSR. The device operates in the normal mode.

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boundary toggle outputs

The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during
Capture-DR. Data in the shift-register elements of the selected output BSCs is toggled on each rising edge of
TCK in Run-Test/Idle, updated in the shadow latches, and applied to the associated device output pins on each
falling edge of TCK in Run-Test/Idle. Data in the selected input BSCs remains constant and is applied to the
inputs of the normal on-chip logic. Data appearing at the device input pins is not captured in the input BSCs.
The device operates in the test mode.

boundary-control-register scan

The BCR is selected in the scan path. The value in the BCR remains unchanged during Capture-DR. This
operation must be performed before a boundary-run test operation to specify which test operation is to be
executed.

boundary-control-register opcode description

The BCR opcodes are decoded from BCR bits 2 0 as shown in Table 5. The selected test operation is
performed while the RUNT instruction is executed in the Run-Test/Idle state. The following descriptions detail
the operation of each BCR instruction and illustrate the associated PSA and PRPG algorithms.

Table 5. Boundary-Control-Register Opcodes

BINARY CODE

BIT 2

BIT 0

MSB

LSB

DESCRIPTION

X00

Sample inputs/toggle outputs (TOPSIP)

X01

Pseudo-random pattern generation/36-bit mode (PRPG)

X10

Parallel-signature analysis/36-bit mode (PSA)

011

Simultaneous PSA and PRPG/18-bit mode (PSA/PRPG)

111

Simultaneous PSA and binary count up/18-bit mode (PSA/COUNT)

While the control input BSCs (bits 87 72) are not included in the toggle, PSA, PRPG, or COUNT algorithms,
the output-enable BSCs (bits 87 84 of the BSR) control the drive state (active or high impedance) of the
selected device output pins. These BCR instructions are valid only when both bytes of the device are operating
in one direction of data flow (that is, 1OEA

1OEB and 2OEA

2OEB) and in the same direction of data flow

(that is, 1OEA

2OEA and 1OEB

2OEB). Otherwise, the bypass instruction is operated.

PSA input masking

Bits 20 3 of the BCR are used to specify device input pins to be masked from PSA operations. Bit 20 selects
masking for device input pin 2A9 during A-to-B data flow or for device input pin 2B9 during B-to-A data flow.
Bit 3 selects masking for device input pins 1A1 or 1B1 during A-to-B or B-to-A data flow, respectively. Bits
intermediate to 20 and 3 mask corresponding device input pins in order from most significant to least significant,
as indicated in Table 2. When the mask bit that corresponds to a particular device input has a logic 1 value, the
device input pin is masked from any PSA operation, meaning that the state of the device input pin is ignored
and has no effect on the generated signature. Otherwise, when a mask bit has a logic 0 value, the corresponding
device input is not masked from the PSA operation.

sample inputs/toggle outputs (TOPSIP)

Data appearing at the selected device input pins is captured in the shift-register elements of the selected BSCs
on each rising edge of TCK. This data is updated in the shadow latches of the selected input BSCs and applied
to the inputs of the normal on-chip logic. Data in the shift-register elements of the selected output BSCs is
toggled on each rising edge of TCK, updated in the shadow latches, and applied to the associated device output
pins on each falling edge of TCK.

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pseudo-random pattern generation (PRPG)

A pseudo-random pattern is generated in the shift-register elements of the selected BSCs on each rising edge
of TCK, updated in the shadow latches, and applied to the associated device output pins on each falling edge
of TCK. This data also is updated in the shadow latches of the selected input BSCs and applied to the inputs
of the normal on-chip logic. Figures 5 and 6 illustrate the 36-bit linear-feedback shift-register algorithms through
which the patterns are generated. An initial seed value should be scanned into the BSR before performing this
operation. A seed value of all zeroes does not produce additional patterns.

1B8-O

1B7-O

1B6-O

1B5-O

1B4-O

1B3-O

1B2-O

1B1-O

1B9-O

1A7-I

1A6-I

1A5-I

1A4-I

1A3-I

1A2-I

1A1-I

1A8-I

1A9-I

2A7-I

2A6-I

2A5-I

2A4-I

2A3-I

2A2-I

2A1-I

2A8-I

2A9-I

2B8-O

2B7-O

2B6-O

2B5-O

2B4-O

2B3-O

2B2-O

2B1-O

2B9-O

Figure 5. 36-Bit PRPG Configuration (1OEA = 2OEA = 0, 1OEB = 2OEB = 1)

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parallel-signature analysis (PSA)

Data appearing at the selected device input pins is compressed into a 36-bit parallel signature in the
shift-register elements of the selected BSCs on each rising edge of TCK. This data is updated in the shadow
latches of the selected input BSCs and applied to the inputs of the normal on-chip logic. Data in the shadow
latches of the selected output BSCs remains constant and is applied to the device outputs. Figures 7 and 8
illustrate the 36-bit linear-feedback shift-register algorithms through which the signature is generated. An initial
seed value should be scanned into the BSR before to performing this operation.

MASKX.X

1B8-O

1B7-O

1B6-O

1B5-O

1B4-O

1B3-O

1B2-O

1B1-O

1B9-O

1A7-I

1A6-I

1A5-I

1A4-I

1A3-I

1A2-I

1A1-I

1A8-I

1A9-I

2A7-I

2A6-I

2A5-I

2A4-I

2A3-I

2A2-I

2A1-I

2A8-I

2A9-I

2B8-O

2B7-O

2B6-O

2B5-O

2B4-O

2B3-O

2B2-O

2B1-O

2B9-O

Figure 7. 36-Bit PSA Configuration (1OEA = 2OEA = 0, 1OEB = 2OEB = 1)

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simultaneous PSA and PRPG (PSA/PRPG)

Data appearing at the selected device input pins is compressed into an 18-bit parallel signature in the
shift-register elements of the selected input BSCs on each rising edge of TCK. This data is updated in the
shadow latches of the selected input BSCs and applied to the inputs of the normal on-chip logic. At the same
time, an 18-bit pseudo-random pattern is generated in the shift-register elements of the selected output BSCs
on each rising edge of TCK, updated in the shadow latches, and applied to the associated device output pins
on each falling edge of TCK. Figures 9 and 10 illustrate the 18-bit linear-feedback shift-register algorithms
through which the signature and patterns are generated. An initial seed value should be scanned into the BSR
before performing this operation. A seed value of all zeroes does not produce additional patterns.

MASKX.X

1B8-O

1B7-O

1B6-O

1B5-O

1B4-O

1B3-O

1B2-O

1B1-O

1B9-O

1A7-I

1A6-I

1A5-I

1A4-I

1A3-I

1A2-I

1A1-I

1A8-I

1A9-I

2A7-I

2A6-I

2A5-I

2A4-I

2A3-I

2A2-I

2A1-I

2A8-I

2A9-I

2B8-O

2B7-O

2B6-O

2B5-O

2B4-O

2B3-O

2B2-O

2B1-O

2B9-O

Figure 9. 18-Bit PSA/PRPG Configuration (1OEA = 2OEA = 0, 1OEB = 2OEB = 1)

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simultaneous PSA and binary count up (PSA/COUNT)

Data appearing at the selected device input pins is compressed into an 18-bit parallel signature in the
shift-register elements of the selected input BSCs on each rising edge of TCK. This data is updated in the
shadow latches of the selected input BSCs and applied to the inputs of the normal on-chip logic. At the same
time, an 18-bit binary count-up pattern is generated in the shift-register elements of the selected output BSCs
on each rising edge of TCK, updated in the shadow latches, and applied to the associated device output pins
on each falling edge of TCK. Figures 11 and 12 illustrate the 18-bit linear-feedback shift-register algorithms
through which the signature is generated. An initial seed value should be scanned into the BSR before
performing this operation.

MASKX.X

1B8-O

1B7-O

1B6-O

1B5-O

1B4-O

1B3-O

1B2-O

1B1-O

1B9-O

1A7-I

1A6-I

1A5-I

1A4-I

1A3-I

1A2-I

1A1-I

1A8-I

1A9-I

2A7-I

2A6-I

2A5-I

2A4-I

2A3-I

2A2-I

2A1-I

2A8-I

2A9-I

2B8-O

2B7-O

2B6-O

2B5-O

2B4-O

2B3-O

2B2-O

2B1-O

2B9-O

MSB

LSB

Figure 11. 18-Bit PSA/COUNT Configuration (1OEA = 2OEA = 0, 1OEB = 2OEB = 1)

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timing description

All test operations of the SN54ABT18646 are synchronous to the TCK signal. Data on the TDI, TMS, and
normal-function inputs is captured on the rising edge of TCK. Data appears on the TDO and normal-function
output pins on the falling edge of TCK. The TAP controller is advanced through its states (as illustrated in
Figure 2) by changing the value of TMS on the falling edge of TCK and then applying a rising edge to TCK.

A simple timing example is illustrated in Figure 13. In this example, the TAP controller begins in the
Test-Logic-Reset state and is advanced through its states as necessary to perform one instruction-register scan
and one data-register scan. While in the Shift-IR and Shift-DR states, TDI is used to input serial data, and TDO
is used to output serial data. The TAP controller is then returned to the Test-Logic-Reset state. Table 6 explains
the operation of the test circuitry during each TCK cycle.

Table 6. Explanation of Timing Example

TCK

CYCLE(S)

TAP STATE

AFTER TCK

DESCRIPTION

Test-Logic-Reset

TMS is changed to a logic 0 value on the falling edge of TCK to begin advancing the TAP controller toward
the desired state.

Run-Test/Idle

Select-DR-Scan

Select-IR-Scan

Capture-IR

The IR captures the 8-bit binary value 10000001 on the rising edge of TCK as the TAP controller exits the
Capture-IR state.

Shift-IR

TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP on
the rising edge of TCK as the TAP controller advances to the next state.

713

Shift-IR

One bit is shifted into the IR on each TCK rising edge. With TDI held at a logic 1 value, the 8-bit binary value
11111111 is serially scanned into the IR. At the same time, the 8-bit binary value 10000001 is serially scanned
out of the IR via TDO. In TCK cycle 13 TMS is changed to a logic 1 value to end the IR scan on the next TCK
cycle. The last bit of the instruction is shifted as the TAP controller advances from Shift-IR to Exit1-IR.

Exit1-IR

TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK.

Update-IR

The IR is updated with the new instruction (BYPASS) on the falling edge of TCK.

Select-DR-Scan

Capture-DR

The bypass register captures a logic 0 value on the rising edge of TCK as the TAP controller exits the
Capture-DR state.

Shift-DR

TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP on
the rising edge of TCK as the TAP controller advances to the next state.

19 20

Shift-DR

The binary value 101 is shifted in via TDI, while the binary value 010 is shifted out via TDO.

Exit1-DR

TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK.

Update-DR

In general, the selected data register is updated with the new data on the falling edge of TCK.

Select-DR-Scan

Select-IR-Scan

Test-Logic-Reset

Test operation completed

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ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

est-Logic-Reset

Run-T

est/Idle

Select-DR-Scan

Select-IR-Scan

Capture-IR

Shift-IR

Exit1-IR

Update-IR

Select-DR-Scan

Capture-DR

Shift-DR

Exit1-DR

Update-DR

Select-DR-Scan

Select-IR-Scan

est-Logic-Reset

TCK

TMS

TDI

TDO

ÎÎÎ

TAP

Controller

State

3-State (TDO) or Don't Care (TDI)

Figure 13. Timing Example

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

(except I/O ports) (see Note 1)

0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

(I/O ports) (see Note 1)

0.5 V to 5.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high state or power-off state, V

0.5 V to 5.5 V

. . . . . . . . . . . . .

Current into any output in the low state, I

96 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

< 0)

18 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, I

< 0)

50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum package power dissipation at T

= 55

C (in still air)

885 mW

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range

C to 150

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

recommended operating conditions (see Note 2)

SN54ABT18646

UNIT

MIN

MAX

UNIT

VCC

Supply voltage

4.5

5.5

VIH

High-level input voltage

VIL

Low-level input voltage

0.8

Input voltage

VCC

IOH

High-level output current

IOL

Low-level output current

t /

Input transition rise or fall rate

10*

ns /V

Operating free-air temperature

125

* Not production tested on products compliant to MIL STD 883D
NOTE 2: Unused or floating pins (input or I/O) must be held high or low.

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electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER

TEST CONDITIONS

TA = 25

SN54ABT18646

UNIT

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

MIN

MAX

UNIT

VIK

VCC = 4.5 V,

II = 18 mA

1.2

VCC = 4.5 V,

IOH = 3 mA

2.5

VOH

VCC = 5 V,

IOH = 3 mA

VOH

VCC = 4.5 V,

IOH = 24 mA

VCC = 4.5 V,

IOH = 32 mA

VOL

VCC = 4 5 V

IOL = 48 mA**

0.55

VOL

VCC = 4.5 V

IOL = 64 mA

0.55*

VCC = 5 5 V

VI = VCC or GND

CLK, DIR, OE, S, TCK

VCC = 5.5 V,

VI = VCC or GND

A or B ports

100

IIH

VCC = 5.5 V,

VI = VCC

TDI, TMS

IIL

VCC = 5.5 V,

VI = GND

TDI, TMS

160

IOZH

VCC = 5.5 V,

VO = 2.7 V

IOZL

VCC = 5.5 V,

VO = 0.5 V

Ioff

VCC = 0,

VI or VO

5.5 V

100*

ICEX

VCC = 5.5 V,

VO = 5.5 V

Outputs high

50*

IO§

VCC = 5.5 V,

VO = 2.5 V

100

180

VCC = 5.5 V,

Outputs high

0.9

5.5

ICC

VCC 5.5 V,
IO = 0,

A or B ports

Outputs low

VI = VCC or GND

Outputs disabled

0.9

VCC = 5 5 V

One input at 3 4 V Other inputs at VCC or GND

1 5

ICC¶

VCC = 5.5 V,

One input at 3.4 V, Other inputs at VCC or GND

1.5

VI = 2.5 V or 0.5 V

Control inputs

5.8

Cio

VO = 2.5 V or 0.5 V

A or B ports

12.2

VO = 2.5 V or 0.5 V

TDO

8.5

* On products compliant to MIL-STD-883, Class B, this parameter does not apply.
** IOL = 24 mA for products compliant to 883D

All typical values are at VCC = 5 V.

The parameters IOZH and IOZL include the input leakage current.

§ Not more than one output should be tested at a time, and the duration of the test should not exceed one second
¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

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timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (normal mode) (see Figure 14)

SN54ABT18646

UNIT

MIN

MAX

UNIT

fclock

Clock frequency

CLKAB or CLKBA

100

MHz

Pulse duration

CLKAB or CLKBA high or low

tsu

Setup time

A before CLKAB

or B before CLKBA

6.2

Hold time

A after CLKAB

or B after CLKBA

0.6

timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (test mode) (see Figure 14)

123

SN54ABT18646

UNIT

MIN

MAX

UNIT

fclock

Clock frequency

TCK

MHz

Pulse duration

TCK high or low

8.2

A, B, CLK, DIR, OE, or S before TCK

6.4

tsu

Setup time

TDI before TCK

7.5

TMS before TCK

A, B, CLK, DIR, OE, or S after TCK

0.7

Hold time

TDI after TCK

0.5

TMS after TCK

0.5

Delay time

Power up to TCK

Rise time

VCC power up

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switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (normal mode) (see Figure 14)

PARAMETER

FROM

(INPUT)

(OUTPUT)

VCC = 5 V,

TA = 25

SN54ABT18646

UNIT

(INPUT)

(OUTPUT)

MIN

TYP

MAX

MIN

MAX

fmax

CLKAB or CLKBA

100

130

100

MHz

tPLH

A or B

B or A

5.1

1.5

5.8

tPHL

A or B

B or A

1.7

6.3

1.4

7.1

tPLH

CLKAB or CLKBA

B or A

2.5

7.5

2.1

8.6

tPHL

CLKAB or CLKBA

B or A

2.5

tPLH

SAB or SBA

B or A

7.1

1.5

tPHL

SAB or SBA

B or A

7.7

8.7

tPZH

DIR

B or A

7.3

1.7

8.5

tPZL

DIR

B or A

8.4

2.5

9.6

tPZH

B or A

7.9

1.8

9.1

tPZL

B or A

2.7

8.6

2.7

9.8

tPHZ

DIR

B or A

3.5

9.4

11.5

tPLZ

DIR

B or A

8.5

2.1

9.4

tPHZ

B or A

3.5

8.9

3.5

tPLZ

B or A

8.1

1.5

9.4

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (test mode) (see Figure 14)

123

PARAMETER

FROM

(INPUT)

(OUTPUT)

VCC = 5 V,

TA = 25

SN54ABT18646

UNIT

(INPUT)

(OUTPUT)

MIN

TYP

MAX

MIN

MAX

fmax

TCK

MHz

tPLH

TCK

A or B

2.5

12.3

2.5

15.3

tPHL

TCK

A or B

2.5

11.8

2.5

14.2

tPLH

TCK

TDO

5.8

tPHL

TCK

TDO

6.6

tPZH

TCK

A or B

4.5

12.1

4.5

15.3

tPZL

TCK

A or B

13.4

16.3

tPZH

TCK

TDO

2.5

1.8

7.5

tPZL

TCK

TDO

7.5

tPHZ

TCK

A or B

tPLZ

TCK

A or B

14.5

17.5

tPHZ

TCK

TDO

8.4

9.5

tPLZ

TCK

TDO

7.6

2.7

SN54ABT18646
SCAN TEST DEVICE WITH
18-BIT TRANSCEIVERS AND REGISTERS

SGBS306 AUGUST 1992 REVISED AUGUST 1994

428

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

1.5 V

tsu

From Output

Under Test

CL = 50 pF

LOAD CIRCUIT FOR OUTPUTS

7 V

Open

GND

500

Data Input

Timing Input

1.5 V

3 V

0 V

1.5 V

3 V

0 V

3 V

0 V

1.5 V

Input

(see Note A)

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NON-INVERTING OUTPUTS

VOLTAGE WAVEFORMS

PULSE DURATION

tPLH

tPHL

tPLH

VOH

VOL

1.5 V

3 V

0 V

1.5 V

Input

(see Note B)

1.5 V

Output

Control

Output

Waveform 1

S1 at 7 V

(see Note C)

Output

Waveform 2

S1 at Open

(see Note C)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

1.5 V

3.5 V

0 V

1.5 V

VOL + 0.3 V

1.5 V

VOH 0.3 V

[

0 V

3 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

Output

tPLH/tPHL

tPLZ/tPZL

tPHZ/tPZH

Open

7 V

Open

TEST

NOTES: A. CL includes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics: PRR

10 MHz, ZO = 50

, tr

2.5 ns, tf

2.5 ns.

C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

D. The outputs are measured one at a time with one transition per measurement.

Figure 14. Load Circuit and Voltage Waveforms

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