SN54ABTH32501, SN74ABTH32501
36-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS229F JUNE 1992 REVISED MAY 1997
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Members of the Texas Instruments
Widebus+
TM
Family
D
State-of-the-Art
EPIC-
B
TM
BiCMOS Design
Significantly Reduces Power Dissipation
D
UBT
TM
(Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D
Released as DSCC SMD 5962-9557601NXD
D
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 5 V, T
A
= 25
C
D
High-Impedance State During Power Up
and Power Down
D
Distributed V
CC
and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
High-Drive Outputs (32-mA I
OH
, 64-mA I
OL
)
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Package Options Include 100-Pin Plastic
Thin Quad Flat (PZ) Package With
14
14-mm Body Using 0.5-mm Lead Pitch
and Space-Saving 100-Pin Ceramic Quad
Flat (HS) Package
'ABTH32501 . . . PZ PACKAGE
(TOP VIEW)
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
2A10
2A9
GND
2A8
2A7
2A6
2A5
GND
2A4
2A3
2A2
2A1
V
CC
1A1
1A2
1A3
1A4
GND
1A5
1A6
1A7
1A8
GND
1A9
1A10
2B10
2B9
GND
2B8
2B7
2B6
2B5
GND
2B4
2B3
2B2
2B1
V
CC
1B1
1B2
1B3
1B4
GND
1B5
1B6
1B7
1B8
GND
1B9
1B10
2A1
1
2A12
2A13
V
CC
2A14
2A15
2A16
2A17
2A18
2OEBA
2LEBA
2CLKBA
2CLKAB
2LEAB
2OEAB
2B18
2B17
2B16
2B15
2B14
GND
2B13
2B12
2B1
1
GND
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1A1
1
1A12
1A13
GND
1A14
1A15
1A16
1A17
1A18
1OEBA
1LEBA
1CLKBA
V
1CLKAB
1LEAB
1OEAB
1B18
1B17
1B16
1B15
1B14
GND
1B13
1B12
1B1
1
CC
The HS package is not production released.
Copyright
1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Widebus+, EPIC-
B, and UBT are trademarks of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54ABTH32501, SN74ABTH32501
36-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS229F JUNE 1992 REVISED MAY 1997
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
GND
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
2B12
2B11
2B9
2B8
2B7
2B6
2B5
GND
2B4
2B3
2B2
2B1
1B1
1B4
GND
1B5
1B6
1B7
1B8
2A13
2A11
2A10
2A9
2A8
2A7
2A6
2A5
2A4
2A3
2A1
1A1
1A2
1A3
1A4
GND
1A5
1A7
1A8
GND
2A14
2A16
2A17
2A18
2B17
2B16
2B15
2B14
GND
GND
1A14
1A15
1A16
1A17
1A18
1OEBA
1B18
1B17
1B16
1B14
GND
1B15
2A12
2OEAB
2B10
1B3
GND
1A6
1A9
1A10
1A11
1A12
GND
1B9
1B10
1B11
1B12
2B18
2A15
SN54ABTH32501 . . . HS PACKAGE
(TOP VIEW)
2A2
V
CC
1LEBA
1CLKBA
CC
V
1CLKAB
1LEAB
1OEAB
1B2
V
CC
GND
2LEAB
2CLKAB
CC
V
2CLKBA
2LEABA
2OEBA
GND
1A13
1B13
2B13
For HS package availability, please contact the factory or your local TI Field Sales Office.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SN54ABTH32501, SN74ABTH32501
36-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS229F JUNE 1992 REVISED MAY 1997
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description
These 36-bit UBTs combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and
clocked modes.
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when
LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is
low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. Data flow for B to A is similar
to that of A to B, but uses OEBA, LEBA, and CLKBA.
Output-enable OEAB is active high. When OEAB is high, the outputs are active. When OEAB is low, the outputs
are in the high-impedance state. The output enables are complementary (OEAB is active high, and OEBA is
active low).
When V
CC
is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE should be tied to V
CC
through a pullup resistor
and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by
the current-sinking/current-sourcing capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN54ABTH32501 is characterized for operation over the full military temperature range of 55
C to 125
C.
The SN74ABTH32501 is characterized for operation from 40
C to 85
C.
FUNCTION TABLE
INPUTS
OUTPUT
OEAB
LEAB
CLKAB
A
B
L
X
X
X
Z
H
H
X
L
L
H
H
X
H
H
H
L
L
L
H
L
H
H
H
L
H
X
B0
H
L
L
X
B0
A-to-B data flow is shown: B-to-A flow is similar, but
uses OEBA, LEBA, and CLKBA.
Output level before the indicated steady-state input
conditions were established
Output level before the indicated steady-state input
conditions were established, provided that CLKAB
was low before LEAB went low
SN54ABTH32501, SN74ABTH32501
36-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS229F JUNE 1992 REVISED MAY 1997
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram (positive logic)
1OEBA
LE
CLK
1OEAB
1LEBA
1CLKBA
1CLKAB
1LEAB
1A1
1B1
To 17 Other Channels
D
LE
CLK
D
2OEBA
LE
CLK
2OEAB
2LEBA
2CLKBA
2CLKAB
2LEAB
2A1
2B1
To 17 Other Channels
D
LE
CLK
D
41
37
36
35
39
40
14
85
89
90
91
87
86
12
62
64
Pin numbers shown are for the PZ package.
SN54ABTH32501, SN74ABTH32501
36-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS229F JUNE 1992 REVISED MAY 1997
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(except I/O ports) (see Note 1)
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or power-off state, V
O
0.5 V to 5.5 V
. . . . . . . . . . . . . . . . . . .
Current into any output in the low state, I
O
: SN54ABTH32501 96
mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ABTH32501 128
mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
18 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): PZ package
50
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
recommended operating conditions (see Note 3)
SN54ABTH32501
SN74ABTH32501
UNIT
MIN
MAX
MIN
MAX
UNIT
VCC
Supply voltage
4.5
5.5
4.5
5.5
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
VI
Input voltage
0
VCC
0
VCC
V
IOH
High-level output current
24
32
mA
IOL
Low-level output current
48
64
mA
t/
v
Input transition rise or fall rate
Outputs enabled
10
10
ns/V
t/
VCC
Power-up ramp rate
200
200
s/V
TA
Operating free-air temperature
55
125
40
85
C
NOTE 3: Unused control pins must be held high or low to prevent them from floating.
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