Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TSB12LV21A
(PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 APRIL 1997
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Supports Provisions of IEEE 1394-1995
(1394) Standard for High-Performance
Serial Bus
D
Performs the Function of a 1394 Cycle
Master
D
Supports 1394 Transfer Rates of 100, 200
and 400 Mbit/s
D
Provides Three Sizes of Programmable
FIFOs
D
Provides PCI Bus Master Function for
Supporting DMA Operations
D
Compliant With PCI Specification 2.1
D
Provides PCI Slave Function for Read/Write
Access of Internal Registers
D
Supports the Plug-and-Play (PnP)
Specification
D
Provides an 8-/16-bit Zoom Video (ZV) Port
for the Transferring of Video Data Directly
to an External Motion Video Memory Area
D
Operates from a 3.3-V Power Supply While
Maintaining 5-V Tolerant Inputs
D
High-Performance 176-Pin PQFP (PGF)
Package
description
The TSB12LV21A (PCILynx) provides a high-performance IEEE 1394-1995 interface with the capability to
transfer data between the 1394 phy-link interface, the PCI bus interface, and external devices connected to the
local bus interface. The 1394 phy-link interface provides the connection to the 1394 physical layer device and
is supported by the on-board link layer controller (LLC). The LLC provides the control for transmitting and
receiving 1394 packet data between the FIFO and phy-link interface at rates of 100 Mbit/s, 200 Mbit/s, and 400
Mbit/s. The link layer also provides the capability to receive status from the physical layer device and to access
the physical layer control and status registers by the application software.
An internal 1K-byte memory is provided that can be configured as multiple variable-size FIFOs and eliminates
the need for external FIFOs. Separate FIFOs can be user configured to support 1394 receive, asynchronous
transmit, and isochronous transmit transfer operations.
The PCI interface supports 32-bit burst transfers up to 33 MHz and is capable of operating as both master and
target devices. Configuration registers can be loaded from an external serial EEPROM, allowing board and
system designers to assign their own unique identification codes. An autoboot mode allows data-moving
systems (such as docking stations) to be designed to operate on the PCI bus without the need for a host CPU.
The DMA controller uses packet control list (PCL) data structures to control the transfer of data and allow the
DMA to operate without host CPU intervention. These PCLs can reside in PCI memory or in memory that is
connected to the local bus port. The PCLs implement an instruction set that allows linking, conditional
branching, 1394 data transfer control, auxiliary support commands, and status reporting. Five DMA channels
are provided to accommodate programmable data types. PCLs can be chained together to form a channel
control program that can be developed to support each DMA channel. Data can be stored in either big endian
or little endian format eliminating the need for the host CPU to perform byte swapping. Data can be transferred
to either 4-byte aligned locations to provide the highest performance or to nonaligned locations to provide the
best memory use.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
1997, Texas Instruments Incorporated
This serial bus implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thomson, Limited.
TSB12LV21A
(PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 APRIL 1997
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
The RAM, ROM, AUX, ZV, and general purpose I/O (GPIO) ports collectively implement the local bus interface.
These ports are mapped into the PCI address can be accessed either through the PCI bus or internal DMA
transactions. Internal transactions do not appear on the external PCI bus, thereby conserving PCI bandwidth.
DMA packet control lists or other data that may be stored in external RAM or ROM attached to the local bus
interface. This further reduces PCI use and generally improves performance. The ZV local bus port is designed
to transfer data from 1394 video devices to an external device connected to the PCILynx ZV port. This interface
provides a method of receiving 1394 digital camera packets directly to a ZV-compliant device attached to the
local bus interface.
Built-in test registers, a dedicated test output terminal, and four GPIO terminals allow observation of internal
states and provides a convenient software debug capability. Programmable interrupts are available to inform
driver software of important events such as 1394 bus resets and DMA-to-PCL transfer completion.
The 3.3-V internal operation provides reduced power consumption while maintaining compatibility with 5-V
signaling environments. The PCI interface is compatible with both 3-V and 5-V PCI systems.
TSB12LV21A
(PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 APRIL 1997
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
30
pci_ad26
GND
pci_ad27
pci_ad28
pci_ad29
pci_ad30
pci_ad31
GND
pci_reqz
pci_intaz
pci_gntz
pci_resetz
pci_clk
GND
autoboot
GND
phy_clk50
GND
32
33
34
35
36
37
38
39
40
31
41
42
43
44
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
GND
NC
pci_ad8
pci_cbez0
pci_ad7
GND
pci_ad5
pci_ad4
pci_ad3
pci_ad2
pci_ad1
pci_ad0
aux_rdy
GND
aux_rstz
aux_intz
CC
V
3.3V
CC
V
3.3V
CC
V
5V
CC
V
5V
aux_clk
pci_ad6
CC
V
3.3V
CC
V
3.3V
CC
V
3.3V
CC
V
5V
pci_ad9
GND
145
146
147
148
149
150
151
152
153
154
132
131
130
129
128
127
126
125
124
123
122
121
143
144
phy_data7
phy_data6
phy_data5
phy_data4
GND
phy_data3
phy_data1
phy_data0
phy_lreq
phy_ctl1
phy_ctl0
GND
test_out
link_cycleout
link_cyclein
seeprom_data
seeprom_clk
93
77
76
75
74
73
72
71
70
69
68
67
78
ram_csz
aux_csz
aux_wez1
GND
aux_wez0
aux_oez
aux_data15
aux_data14
87
86
85
84
83
82
81
80
79
88
GND
aux_data12
aux_data1
1
aux_data10
aux_data9
aux_data7
aux_data8
92
91
90
89
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
133
134
135
136
137
138
139
140
141
142
CC
V
3.3V
CC
V
5V
CC
V
3.3V
CC
V
3.3V
CC
V
3.3V
CC
V
5V
aux_data13
aux_data6
rom_csz
CC
V
3.3V
phy_data2
CC
V
3.3V
GND
GND
NC No internal connection
PGF PACKAGE
(TOP VIEW)
3.3V VCC
NC
pci_ad25
pci_ad24
pci_cbez3
pci_idselz
3.3V VCC
pci_ad23
pci_ad22
pci_ad21
5V VCC
pci_ad20
GND
pci_ad19
pci_ad18
pci_ad17
pci_ad16
3.3V VCC
pci_cbez2
GND
pci_framez
pci_irdyz
pci_trdyz
pci_devselz
3.3V VCC
pci_stopz
GND
NC
pci_perrz
pci_serrz
pci_par
3.3V VCC
pci_cbez1
pci_ad15
GND
pci_ad14
pci_ad13
pci_ad12
5V VCC
pci_ad11
3.3V VCC
pci_ad10
zv_data_valid
zv_hsync
GND
zv_ext_clk
3.3V VCC
zv_vsync
zv_pix_clk
gpio_data0
gpio_data1
gpio_data2
gpio_data3
GND
GND
NC
aux_adr0
aux_adr1
aux_adr2
3.3V VCC
aux_adr3
aux_adr4
aux_adr5
aux_adr6
aux_adr7
5V VCC
aux_adr8
3.3V VCC
aux_adr9
aux_adr10
aux_adr11
aux_adr12
aux_adr13
3.3V VCC
aux_adr14
aux_data1
aux_data0
aux_adr15
GND
aux_data2
3.3V VCC
aux_data3
aux_data4
aux_data5
TSB12LV21A
(PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 APRIL 1997
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
Terminal
I/O
Description
Name
No.
I/O
Description
3.3V V
CC
1,8,19,26,33,42,49
56,70,75,86,93,100
107,116,128,136,138,
145,157,165,172
I
3.3-V power input
5V V
CC
12,40,60,63
84,109,135,162
I
5-V tolerant power input. When interfacing with a 3.3-V parts, these termi-
nals should be connected to 3.3-V power.
autoboot
159
I
Autoboot to select autoboot mode
aux_adr150
98,99,101,103106
108,110113,115
117119
O
Auxiliary port address lines
aux_clk
64
O
Auxiliary port clock out (output at frequency of PCI clock)
aux_csz
69
O
Auxiliary port chip select
aux_data150
7678,8083,85,87
88,9092,94,96,97
I/O
Auxiliary port bidirectional data bus to external logic
aux_intz
61
I
Auxiliary port interrupt
aux_oez
74
O
Auxiliary port output enable
aux_rdy
62
I
Auxiliary port ready indication (from external logic)
aux_rstz
66
O
Auxiliary port reset out
aux_wez10
71,73
O
Auxiliary port write strobes (to external logic)
GND
6,14,21,28,35,45
51,65,72,79,89,95
102,114,121,130,141
150,155,158,160,168
175
I
Ground
gpio_data30
122125
I/O
Auxiliary port general purpose programmable I/O signals
link_cyclein
137
I
Optional external 8-kHz clock
link_cycleout
139
O
Cycle timer 8-kHz cycle clock out
N/C
2,29,46,120
Not connected
pci_ad310
169171,173,174,176
3,4,911,13,1518
3639,41,43,44,47,50
5255,5759
I/O
PCI multiplexed address/data bus signals
pci_cbez30
5,20,34,48
I/O
PCI multiplexed command/byte enable signals
pci_clk
161
I
PCI system clock
pci_devselz
25
I/O
PCI device select
pci_framez
22
I/O
PCI frame signal
TSB12LV21A
(PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
SLLS273 APRIL 1997
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (continued)
Terminal
I/O
Description
Name
No.
I/O
Description
pci_gntz
164
I
PCI bus grant signal (from PCI bus arbiter)
pci_idselz
7
I/O
PCI initialization device select
pci_intaz
166
OD
PCI system interrupt A. This is an open drain signal.
pci_irdyz
23
I/O
PCI initiator-ready signal
pci_par
32
I/O
PCI parity signal
pci_perrz
30
I/O
PCI data-parity-error signal
pci_reqz
167
O
PCI master bus request (to PCI bus arbiter)
pci_resetz
163
I
PCI system reset
pci_serrz
31
OD
PCI system-error signal. This is an open drain signal.
pci_stopz
27
I/O
PCI stop signal
pci_trdyz
24
I/O
PCI target-ready signal
phy_clk50
156
I
50-MHz system clock (from PHY chip)
phy_ctl0 1
142,143
I/O
Phy-link bidirectional control lines
phy_data07
146149,151154
I/O
Phy-link bidirectional data lines
phy_lreq
144
O
Phy-link request signal
ram_csz
67
O
External RAM chip select
rom_csz
68
O
External ROM chip select
seeprom_clk
133
I/O
External serial EEPROM data clock
seeprom_data
134
I/O
External serial EEPROM read/write data line
test_out
140
O
Test MUX out
zv_data_valid
132
O
Zoom port data-valid signal
zv_ext_clk
129
I
Zoom port external clock input
zv_hsync
131
O
Zoom port horizontal-sync output
zv_pix_clk
126
O
Zoom port pixel clock
zv_vsync
127
O
Zoom port vertical-sync output
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