SN54F109, SN74F109
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SDFS047A MARCH 1987 REVISED OCTOBER 1993
Copyright
1993, Texas Instruments Incorporated
21
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
description
These devices contain two independent J-K
positive-edge-triggered flip-flops. A low level at
the preset (PRE) or clear (CLR) inputs sets or
resets the outputs regardless of the levels of the
other inputs. When PRE and CLR are inactive
(high), data at the J and K input meeting the
setup-time requirements are transferred to the
outputs on the positive-going edge of the clock
pulse. Clock triggering occurs at a voltage level
and is not directly related to the rise time of the
clock pulse. Following the hold time interval, data
at the J and K inputs may be changed without
affecting the levels at the outputs. These versatile
flip-flops can perform as toggle flip-flops by
grounding K and trying J high. They also can
perform as D-type flip-flops if J and K are tied
together.
The SN54F109 is characterized for operation over
the full military temperature range of 55
C to
125
C. The SN74F109 is characterized for
operation from 0
C to 70
C.
FUNCTION TABLE
INPUTS
OUTPUTS
PRE
CLR
CLK
J
K
Q
Q
L
H
X
X
X
H
L
H
L
X
X
X
L
H
L
L
X
X
X
H
H
H
H
L
L
L
H
H
H
H
L
Toggle
H
H
L
H
Q0
Q0
H
H
H
H
H
L
H
H
L
X
X
Q0
Q0
The output levels are not guaranteed to meet the minimum
levels for VOH. Furthermore, this configuration is nonstable;
that is, it will not persist when PRE or CLR returns to its
inactive (high) level.
SN54F109 . . . J PACKAGE
SN74F109 . . . D OR N PACKAGE
(TOP VIEW)
SN54F109 . . . FK PACKAGE
(TOP VIEW)
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
2J
2K
NC
2CLK
2PRE
1K
1CLK
NC
1PRE
1Q
1J
1CLR
NC
2Q
2Q
V
2CLR
1Q
GND
NC
CC
NC No internal connection
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1CLR
1J
1K
1CLK
1PRE
1Q
1Q
GND
VCC
2CLR
2J
2K
2CLK
2PRE
2Q
2Q
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN54F109, SN74F109
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SDFS047A MARCH 1987 REVISED OCTOBER 1993
22
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic symbol
S
5
1J
2
1J
4
1CLK
1K
3
1Q
6
7
C1
11
14
2J
12
2CLK
13
2Q
10
9
1PRE
2PRE
1CLR
2K
1Q
2Q
R
1
1K
15
2CLR
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
1.2 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current range
30 mA to 5 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state
0.5 V to V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the low state
40 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range: SN54F109
55
C to 125
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74F109
0
C to 70
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input voltage ratings may be exceeded provided the input current ratings are observed.
recommended operating conditions
SN54F109
SN74F109
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
VCC
Supply voltage
4.5
5
5.5
4.5
5
5.5
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
IIK
Input clamp current
18
18
mA
IOH
High-level output current
1
1
mA
IOL
Low-level output current
20
20
mA
TA
Operating free-air temperature
55
125
0
70
C
SN54F109, SN74F109
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SDFS047A MARCH 1987 REVISED OCTOBER 1993
23
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54F109
SN74F109
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
VIK
VCC = 4.5 V,
II = 18 mA
1.2
1.2
V
VOH
VCC = 4.5 V,
IOH = 1 mA
2.5
3.4
2.5
3.4
V
VOH
VCC = 4.75 V,
IOH = 1 mA
2.7
V
VOL
VCC = 4.5 V,
IOL = 20 mA
0.3
0.5
0.3
0.5
V
II
VCC = 5.5 V,
VI = 7 V
0.1
0.1
mA
IIH
VCC = 5.5 V,
VI = 2.7 V
20
20
A
IIL
J, K, CLK
VCC = 5 5 V
VI = 0 5 V
0.6
0.6
mA
IIL
PRE or CLR
VCC = 5.5 V,
VI = 0.5 V
1.8
1.8
mA
IOS
VCC = 5.5 V,
VO = 0
60
150
60
150
mA
ICC
VCC = 5.5 V,
See Note 2
11.7
17
11.7
17
mA
All typical values are at VCC = 5 V, TA = 25
C.
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
NOTE 2: ICC is measured with J, K, CLK, and PRE grounded then with J, K, CLK, and CLR grounded.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
VCC = 5 V,
TA = 25
C
SN54F109
SN74F109
UNIT
F74
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
fclock
Clock frequency
0
100
0
70
0
90
MHz
t
Pulse duration
CLK high, PRE or CLR low
4
4
4
ns
tw
Pulse duration
CLK low
5
5
5
ns
Setup time data before CLK
High
3
3
3
tsu
Setup time, data before CLK
Low
3
3
3
ns
su
Setup time, inactive-state before CLK
PRE or CLR to CLK
2
2
2
th
Hold time data after CLK
High
1
1
1
ns
th
Hold time, data after CLK
Low
1
1
1
ns
Inactive-state setup time is also referred to as recovery time.
switching characteristics (see Note 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
CL = 50 pF,
RL = 500
,
TA = 25
C
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500
,
TA = MIN to MAX
UNIT
(INPUT)
(OUTPUT)
F109
SN54F109
SN74F109
MIN
TYP
MAX
MIN
MAX
MIN
MAX
fmax
100
150
70
90
MHz
tPLH
CLK
Q or Q
3
4.9
7
3
9
3
8
ns
tPHL
CLK
Q or Q
3.6
5.8
8
3.6
10.5
3.6
9.2
ns
tPLH
PRE or CLR
Q or Q
2.4
4.8
7
2.4
9
2.4
8
ns
tPHL
PRE or CLR
Q or Q
2.7
6.6
9
2.7
11.5
2.7
10.5
ns
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
NOTE 3: Load circuits and waveforms are shown in Section 1.
SN54F109, SN74F109
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SDFS047A MARCH 1987 REVISED OCTOBER 1993
24
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
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Copyright
1998, Texas Instruments Incorporated
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