74AC11138
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
SCAS042B MAY 1988 REVISED APRIL 1996
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
D
Designed Specifically for High-Speed
Memory Decoders and Data Transmission
Systems
D
Incorporates Three Enable Inputs to
Simplify Cascading and/or Data Reception
D
Center-Pin V
CC
and GND Configurations
Minimize High-Speed Switching Noise
D
EPIC
TM
(Enhanced-Performance Implanted
CMOS) 1-
m Process
D
500-mA Typical Latch-Up Immunity at
125
C
D
Package Options Include Plastic
Small-Outline (D) and Thin Shrink
Small-Outline (PW) Packages, and
Standard Plastic 300-mil DIPs (N)
description
The 74AC11138 circuit is designed to be used in high-performance memory-decoding or data-routing
applications requiring very short propagation delay times. In high-performance memory systems, this decoder
can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing
a fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than
the typical access time of the memory. This means that the effective system delay introduced by the decoder
is negligible.
The conditions at the binary-select (A, B, C) inputs and the three enable (G1, G2A, G2B) inputs select one of
eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or
inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line
decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.
The 74AC11138 is characterized for operation from 40
C to 85
C.
FUNCTION TABLE
ENABLE INPUTS
SELECT INPUTS
OUTPUTS
G1
G2A
G2B
C
B
A
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
X
H
X
X
X
X
H
H
H
H
H
H
H
H
X
X
H
X
X
X
H
H
H
H
H
H
H
H
L
X
X
X
X
X
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
L
H
H
H
H
H
H
H
L
L
L
H
L
H
H
L
H
H
H
H
H
H
L
L
L
H
H
H
H
H
L
H
H
H
H
H
L
L
H
L
L
H
H
H
H
L
H
H
H
H
L
L
H
L
H
H
H
H
H
H
L
H
H
H
L
L
H
H
L
H
H
H
H
H
H
L
H
H
L
L
H
H
H
H
H
H
H
H
H
H
L
Copyright
1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Y1
Y2
Y3
GND
Y4
Y5
Y6
Y7
Y0
A
B
C
V
CC
G1
G2A
G2B
D, N, OR PW PACKAGE
(TOP VIEW)
74AC11138
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
SCAS042B MAY 1988 REVISED APRIL 1996
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
logic symbols (alternatives)
BIN/OCT
1
15
A
2
14
B
4
13
C
10
9
11
G1
Y0
16
0
&
EN
Y1
1
1
Y2
2
2
Y3
3
3
Y4
5
4
Y5
6
5
Y6
7
6
Y7
8
7
DMUX
0
15
A
14
B
2
13
C
10
9
11
G1
Y0
16
0
&
Y1
1
1
Y2
2
2
Y3
3
3
Y4
5
4
Y5
6
5
Y6
7
6
Y7
8
7
G
7
0
G2A
G2B
G2A
G2B
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
G1
G2B
G2A
C
B
A
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Data
Outputs
Select
Inputs
Enable
Inputs
15
14
13
10
9
11
16
1
2
3
5
6
7
8
74AC11138
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
SCAS042B MAY 1988 REVISED APRIL 1996
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
200 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at T
A
= 55
C (in still air) (see Note 2): D package
1.3 W
. . . . . . . . . . . . . . . . . . . .
N package
1.1 W
. . . . . . . . . . . . . . . . . . . .
PW package
0.5 W
. . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150
_
C and a board trace length of 750 mils,
except for the N package, which has a trace length of zero.
recommended operating conditions
MIN
NOM
MAX
UNIT
VCC
Supply voltage
3
5
5.5
V
VCC = 3 V
2.1
VIH
High-level input voltage
VCC = 4.5 V
3.15
V
VCC = 5.5 V
3.85
VCC = 3 V
0.9
VIL
Low-level input voltage
VCC = 4.5 V
1.35
V
VCC = 5.5 V
1.65
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
VCC = 3 V
4
IOH
High-level output current
VCC = 4.5 V
24
mA
VCC = 5.5 V
24
VCC = 3 V
12
IOL
Low-level output current
VCC = 4.5 V
24
mA
VCC = 5.5 V
24
t/
v
Input transition rise or fall rate
0
10
ns/V
TA
Operating free-air temperature
40
85
C
74AC11138
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
SCAS042B MAY 1988 REVISED APRIL 1996
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
MIN
MAX
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
UNIT
3 V
2.9
2.9
IOH = 50
A
4.5 V
4.4
4.4
5.5 V
5.4
5.4
VOH
IOH = 4 mA
3 V
2.58
2.48
V
I
24
A
4.5 V
3.94
3.8
IOH = 24 mA
5.5 V
4.94
4.8
IOH = 75 mA
5.5 V
3.85
3 V
0.1
0.1
IOL = 50
A
4.5 V
0.1
0.1
5.5 V
0.1
0.1
VOL
IOL = 12 mA
3 V
0.36
0.44
V
IOL = 24 mA
4.5 V
0.36
0.44
IOL = 24 mA
5.5 V
0.36
0.44
IOL = 75 mA
5.5 V
1.65
II
VI = VCC or GND
5.5 V
0.1
1
A
ICC
VI = VCC or GND,
IO = 0
5.5 V
4
40
A
Ci
VI = VCC or GND
5 V
3.5
pF
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
switching characteristics over recommended operating free-air temperature range,
V
CC
= 3.3 V
0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25
C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
UNIT
tPLH
A B C
Any Y
1.5
8.3
10.2
1.5
11.4
ns
tPHL
A, B, C
Any Y
1.5
8.9
10.9
1.5
12.2
ns
tPLH
G1
Any Y
1.5
7.2
9.2
1.5
10.2
ns
tPHL
G1
Any Y
1.5
7.3
9.4
1.5
10.5
ns
tPLH
G2A G2B
Any Y
1.5
8.2
10.4
1.5
11.5
ns
tPHL
G2A, G2B
Any Y
1.5
8.3
10.4
1.5
11.6
ns
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25
C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
UNIT
tPLH
A B C
Any Y
1.5
5.7
7.3
1.5
8.1
ns
tPHL
A, B, C
Any Y
1.5
6.2
7.9
1.5
8.8
ns
tPLH
G1
Any Y
1.5
5.1
6.9
1.5
7.5
ns
tPHL
G1
Any Y
1.5
5.2
6.9
1.5
7.7
ns
tPLH
G2A G2B
Any Y
1.5
5.8
7.6
1.5
8.3
ns
tPHL
G2A, G2B
Any Y
1.5
5.6
7.5
1.5
8.3
ns
74AC11138
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
SCAS042B MAY 1988 REVISED APRIL 1996
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
operating characteristics, V
CC
= 5 V, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Cpd
Power dissipation capacitance per gate
CL = 50 pF,
f = 1 MHz
51
pF
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
LOAD CIRCUIT
Input
(see Note B)
50% VCC
50% VCC
tPHL
tPLH
VCC
Output
VOL
VOH
0 V
From Output
Under Test
CL = 50 pF
(see Note A)
500
NOTES: A. CL includes probe and jig capacitance.
B. Input pulses are supplied by generators having the following characteristics: PRR
1 MHz, ZO = 50
, tr = 3 ns, tf = 3 ns.
C. The outputs are measured one at a time with one input transition per measurement.
50% VCC
50% VCC
Figure 1. Load Circuit and Voltage Waveforms
74AC11138
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
SCAS042B MAY 1988 REVISED APRIL 1996
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
APPLICATION INFORMATION
BIN/OCT
1
15
A0
2
14
A1
4
13
A3
10
9
11
0
16
0
&
EN
1
1
1
2
2
2
3
3
3
4
5
4
5
6
5
6
7
6
7
8
7
74AC11138
VCC
BIN/OCT
1
15
2
14
4
13
10
9
11
8
16
0
&
EN
9
1
1
10
2
2
11
3
3
12
5
4
13
6
5
14
7
6
15
8
7
74AC11138
BIN/OCT
1
15
2
14
4
13
10
9
11
16
16
0
&
EN
17
1
1
18
2
2
19
3
3
20
5
4
21
6
5
22
7
6
23
8
7
74AC11138
A2
A4
Figure 2. 24-Bit Decoding Scheme
74AC11138
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
SCAS042B MAY 1988 REVISED APRIL 1996
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
APPLICATION INFORMATION
VCC
BIN/OCT
1
15
A0
2
14
A1
4
13
A3
10
9
11
0
16
0
&
EN
1
1
1
2
2
2
3
3
3
4
5
4
5
6
5
6
7
6
7
8
7
74AC11138
A2
A4
BIN/OCT
1
15
2
14
4
13
10
9
11
8
16
0
&
EN
9
1
1
10
2
2
11
3
3
12
5
4
13
6
5
14
7
6
15
8
7
74AC11138
BIN/OCT
1
15
2
14
4
13
10
9
11
16
16
0
&
EN
17
1
1
18
2
2
19
3
3
20
5
4
21
6
5
22
7
6
23
8
7
74AC11138
BIN/OCT
1
15
2
14
4
13
10
9
11
24
16
0
&
EN
25
1
1
26
2
2
27
3
3
28
5
4
29
6
5
30
7
6
31
8
7
74AC11138
Figure 3. 32-Bit Decoding Scheme
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL
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TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
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Copyright
1998, Texas Instruments Incorporated
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