74AC11160
SYNCHRONOUS 4-BIT DECADE COUNTER
SCAS380 D3199, AUGUST 1988 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Copyright
1993, Texas Instruments Incorporated
1
Internal Look-Ahead for Fast Counting
Carry Output for n-Bit Cascading
Fully Synchronous Operation for Counting
Flow-Through Architecture to Optimize PCB
Layout
Center-Pin V
CC
and GND Pin Configurations
Minimize High-Speed Switching Noise
EPIC
TM
(Enhanced-Performance Implanted
CMOS) 1-
m Process
500-mA Typical Latch-Up Immunity at 125
C
Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
description
This synchronous, presettable 4-bit decade counter features an internal carry look-ahead circuitry for
application in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked
simultaneously so that the outputs change coincident with each other when so instructed by the count-enable
inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally
associated with asynchronous (ripple clock) counters; however, counting spikes may occur on the ripple carry
out output (RCO). A buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the clock
input waveform.
This counter is fully programmable in that they may be preset to any number between 0 and 9. As presetting
is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree
with the setup data after the next clock pulse, regardless of the levels of the enable inputs. The clear function
for the 74AC11160 is synchronous and a low level at the clear input sets all four of the flip-flops outputs low,
regardless of the levels of the clock, load, or enable inputs.
If one of these decade counters is preset to a number between 10 and 15 or assumes such an invalid state when
power is applied, it will progress to the normal sequence within two counts as shown in the state diagram.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry
output. Both count-enable inputs (ENP and ENT) must be high to count, and ENT is fed forward to enable the
ripple carry output (RCO). RCO thus enabled will produce a high-level pulse while the count is 9 (HLLH). This
high-level overflow ripple carry pulse can be used to enable successive cascaded stages. Transitions at the
ENP or ENT are allowed regardless of the level of the clock input.
This counter features a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that will
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions meeting
the setup and hold times.
The 74AC11160 is characterized for operation from 40
C to 85
C.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
RCO
Q
A
Q
B
GND
GND
GND
GND
Q
C
Q
D
LOAD
CLR
CLK
A
B
V
CC
V
CC
C
D
ENP
ENT
DW OR N PACKAGE
(TOP VIEW)
EPIC is a trademark of Texas Instruments Incorporated.
74AC11160
SYNCHRONOUS 4-BIT DECADE COUNTER
SCAS380 D3199, AUGUST 1988 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
2
state diagram
0
1
2
3
4
13
14
15
7
6
5
12
11
10
9
8
logic symbol
CT = 0
A
B
C
D
[1]
QD
QC
QB
QA
2
3
8
9
10
18
17
14
13
ENT
ENP
CLK
M1
M2
G3
G4
C5/2,3,4+
RCO
CTRDIV10
3CT = 9
[2]
[4]
[8]
1,5D
1
20
11
12
19
CLR
LOAD
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
74AC11160
SYNCHRONOUS 4-BIT DECADE COUNTER
SCAS380 D3199, AUGUST 1988 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
3
logic diagram (positive logic)
LOAD
CLR
R
1, 2T/1C3
ENT
ENP
CLK
A
B
C
D
9
8
3
2
1
CK
LD
10
11
12
19
20
18
17
14
13
G2
QA
QB
QC
QD
1, 2T/1C3
1, 2T/1C3
1, 2T/1C3
M1
G4
3D
4R
G2
M1
G4
3D
4R
G2
M1
G4
3D
4R
G2
M1
G4
3D
4R
RCO
74AC11160
SYNCHRONOUS 4-BIT DECADE COUNTER
SCAS380 D3199, AUGUST 1988 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
4
output sequence
Illustrated below is the following sequence:
1. Clear outputs to zero (54AC11160 and 74AC11160 are synchronous)
2. Preset to BCD seven
3. Count to eight, nine, zero, one, two, and three
4. Inhibit.
CLR
LOAD
Data
Inputs
Outputs
QA
QB
QC
QD
7
8
9
CLK
D
C
B
A
Preset
ENP
ENT
RCO
Count
0
1
2
3
Async
Clear
Sync
Clear
Inhibit
74AC11160
SYNCHRONOUS 4-BIT DECADE COUNTER
SCAS380 D3199, AUGUST 1988 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
5
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND pins
125 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
recommended operating conditions (see Note 2)
MIN
NOM
MAX
UNIT
VCC
Supply voltage
3
5
5.5
V
VCC = 3 V
2.1
VIH
High-level input voltage
VCC = 4.5 V
3.15
V
VCC = 5.5 V
3.85
VCC = 3 V
0.9
VIL
Low-level input voltage
VCC = 4.5 V
1.35
V
VCC = 5.5 V
1.65
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
VCC = 3 V
4
IOH
High-level output current
VCC = 4.5 V
24
mA
VCC = 5.5 V
24
VCC = 3 V
12
IOL
Low-level output current
VCC = 4.5 V
24
mA
VCC = 5.5 V
24
t/
v
Input transition rise or fall rate
0
10
ns/ V
TA
Operating free-air temperature
40
85
C
NOTE 2: Unused or floating inputs must be held high or low.
74AC11160
SYNCHRONOUS 4-BIT DECADE COUNTER
SCAS380 D3199, AUGUST 1988 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
6
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
MIN
MAX
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
UNIT
3 V
2.9
2.9
IOH = 50
A
4.5 V
4.4
4.4
5.5 V
5.4
5.4
VOH
IOH = 4 mA
3 V
2.58
2.48
V
I
24
A
4.5 V
3.94
3.8
IOL = 24 mA
5.5 V
4.94
4.8
IOH = 75 mA
5.5 V
3.85
3 V
0.1
0.1
IOL = 50
A
4.5 V
0.1
0.1
5.5 V
0.1
0.1
VOL
IOL = 12 mA
3 V
0.36
0.44
V
IOL = 24 mA
4.5 V
0.36
0.44
IOL = 24 mA
5.5 V
0.36
0.44
IOL = 75 mA
5.5 V
1.65
II
VI = VCC or GND
5.5 V
0.1
1
A
ICC
VI = VCC or GND,
IO = 0
5.5 V
8
80
A
Ci
VI = VCC or GND
5 V
3.5
pF
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
timing requirements, V
CC
= 3.3 V
0.3 V (see Figure 1)
TA = 25
C
MIN
MAX
UNIT
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
0
66
0
66
MHz
t
Pulse duration
CLK low or high
7.5
7.5
ns
tw
Pulse duration
CLR low
6
6
ns
A, B, C, D
6.5
6.5
t
Setup time before CLK
LOAD
6.5
6.5
ns
tsu
Setup time before CLK
ENT, ENP
6
6
ns
CLR inactive
6
6
th
Hold time after CLK
1
1
ns
timing requirements, V
CC
= 5 V
0.5 V (see Figure 1)
TA = 25
C
MIN
MAX
UNIT
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
0
110
0
110
MHz
t
Pulse duration
CLK low or high
4.5
4.5
ns
tw
Pulse duration
CLR low
4.5
4.5
ns
A, B, C, D
3.5
3.5
ns
t
Setup time before CLK
LOAD
6.5
6.5
ns
tsu
Setup time before CLK
ENT, ENP
4.5
4.5
ns
CLR inactive
6
6
ns
th
Hold time after CLK
1
1
ns
74AC11160
SYNCHRONOUS 4-BIT DECADE COUNTER
SCAS380 D3199, AUGUST 1988 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
7
switching characteristics over recommended operating free-air temperature range,
V
CC
= 3.3 V
0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25
C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
UNIT
fmax
66
66
MHz
tPLH
CLK
RCO
1.5
11.2
13.6
1.5
15.2
ns
tPHL
CLK
RCO
1.5
12.2
15.1
1.5
17.2
ns
tPLH
CLK (LOAD high)
Any Q
1.5
9
11.2
1.5
12.5
ns
tPHL
CLK (LOAD high)
Any Q
1.5
10.6
13.4
1.5
15.1
ns
tPLH
CLK (LOAD lo )
Any Q
1.5
8.6
10.8
1.5
12.1
ns
tPHL
CLK (LOAD low)
Any Q
1.5
10.1
12.8
1.5
14.4
ns
tPLH
ENT
RCO
1.5
6
7.6
1.5
8.3
ns
tPHL
ENT
RCO
1.5
6.8
8.9
1.5
9.9
ns
tPLH
CLR
Any Q
1.5
12
15.2
1.5
17.3
ns
tPHL
CLR
RCO
1.5
14.1
17.3
1.5
19.7
ns
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25
C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
UNIT
fmax
110
110
MHz
tPLH
CLK
RCO
1.5
7.8
9.5
1.5
10.7
ns
tPHL
CLK
RCO
1.5
8.5
10.6
1.5
12.1
ns
tPLH
CLK (LOAD high)
Any Q
1.5
6.3
8
1.5
8.9
ns
tPHL
CLK (LOAD high)
Any Q
1.5
7.4
9.8
1.5
11.2
ns
tPLH
CLK (LOAD lo )
Any Q
1.5
6
7.5
1.5
8.4
ns
tPHL
CLK (LOAD low)
Any Q
1.5
7.1
9.4
1.5
10.7
ns
tPLH
ENT
RCO
1.5
4.2
5.5
1.5
6
ns
tPHL
ENT
RCO
1.5
5
6.7
1.5
7.5
ns
tPLH
CLR
Any Q
1.5
8.2
10.7
1.5
12.1
ns
tPHL
CLR
RCO
1.5
9.9
12.2
1.5
13.8
ns
operating characteristics, V
CC
= 5 V, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Cpd
Power dissipation capacitance
CL = 50 pF, f = 1 MHz
48
pF
74AC11160
SYNCHRONOUS 4-BIT DECADE COUNTER
SCAS380 D3199, AUGUST 1988 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
8
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
500
LOAD CIRCUIT
Input
(see Note B)
In-Phase
Output
Out-of-Phase
Output
tPLH
tPHL
tPHL
tPLH
PROPAGATION DELAY TIMES
VOH
VOH
VOL
VOL
50% VCC
0 V
0 V
0 V
High-Level
Input
Low-Level
Input
tw
PULSE DURATION
50%
VCC
0 V
0 V
th
tsu
SETUP AND HOLD TIMES
Data
Input
Timing Input
(see Note B)
50% VCC
50% VCC
50% VCC
50%
50%
VCC
VCC
50%
50%
50%
50%
VCC
VCC
50%
50%
NOTES: A. CL includes probe and jig capacitance.
B. Input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr = 3 ns, tf = 3 ns. For testing
fmax and pulse duration: tr = 1 to 3 ns, tf = 1 to 3 ns.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL
APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER'S RISK.
In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI's publication of information regarding any third
party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright
1998, Texas Instruments Incorporated
PDF 
ZIP