74AC11286
9-BIT PARITY GENERATOR/CHECKER
WITH BUS DRIVER PARITY I/O PORTS
SCAS068A AUGUST 1988 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Copyright
1993, Texas Instruments Incorporated
21
Generates Either Odd or Even Parity for
Nine Data Lines
Cascadable for n-Bits Parity
Direct Bus Connection for Parity
Generation or for Checking by Using the
Parity I/O Port
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin V
CC
and GND Configurations
Minimize High-Speed Switching Noise
EPIC
t
(Enhanced-Performance Implanted
CMOS) 1-
m
m Process
500-mA Typical Latch-Up Immunity
at 125
C
Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
description
The 74AC11286 universal 9-bit parity generator/checker features a local output for parity checking and a
bus-driving parity I/O port for parity generation/checking. The word-length capability is easily expanded by
cascading.
The XMIT control input is implemented specifically to accommodate cascading. When the XMIT is low, the parity
tree is disabled and the PARITY ERROR output will remain at a high logic level regardless of the input levels.
When XMIT is high, the parity tree is enabled. The PARITY ERROR output will indicate a parity error when either
an even number of inputs (A through I) are high and PARITY I/O is forced to a low logic level, or when an odd
number of inputs are high and PARITY I/O is forced to a high logic level.
The I/O control circuitry was designed so that the I/O port will remain in the high-impedance state during power
up or power down to prevent bus glitches.
The 74AC11286 is characterized for operation from 40
C to 85
C.
FUNCTION TABLE
NUMBER OF INPUTS
(A THRU I) THAT
ARE HIGH
XMIT
INPUT
PARITY
I/O
PARITY
ERROR
OUTPUT
0, 2, 4, 6, 8
l
H
H
1, 3, 5, 7, 9
l
L
H
0 2 4 6 8
h
h
H
0, 2, 4, 6, 8
h
l
L
1 3 5 7 9
h
h
L
1, 3, 5, 7, 9
h
l
H
h -- high input level
l -- low input level
H -- high output level
L -- low output level
1
2
3
4
5
6
7
14
13
12
11
10
9
8
B
A
PARITY I/O
GND
PARITY ERROR
XMIT
I
C
D
E
V
CC
F
G
H
D OR N PACKAGE
(TOP VIEW)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
EPIC is a trademark of Texas Instruments Incorporated.
74AC11286
9-BIT PARITY GENERATOR/CHECKER
WITH BUS DRIVER PARITY I/O PORTS
SCAS068A AUGUST 1988 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
22
logic symbol
2k
2, 1
N2
1
EN 1
XMIT
I
H
G
F
E
D
C
B
A
6
7
8
9
10
12
13
14
1
2
PARITY ERROR
PARITY I/O
5
3
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
XMIT
I/O
PARITY
I
H
G
F
E
D
C
B
A
6
3
7
8
9
10
12
13
14
1
2
ERROR
PARITY
5
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
100 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
74AC11286
9-BIT PARITY GENERATOR/CHECKER
WITH BUS DRIVER PARITY I/O PORTS
SCAS068A AUGUST 1988 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
23
recommended operating conditions
MIN
NOM
MAX
UNIT
VCC
Supply voltage
3
5.5
V
VCC = 3 V
2.1
VIH
High-level input voltage
VCC = 4.5 V
3.15
V
VCC = 5.5 V
3.85
VCC = 3 V
0.9
VIL
Low-level input voltage
VCC = 4.5 V
1.35
V
VCC = 5.5 V
1.65
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
VCC = 3 V
4
IOH
High-level output current
VCC = 4.5 V
24
mA
VCC = 5.5 V
24
VCC = 3 V
12
IOL
Low-level output current
VCC = 4.5 V
24
mA
VCC = 5.5 V
24
D
t /
D
v
Input transition rise or fall rate
0
10
ns/ V
TA
Operating free-air temperature
40
85
C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
MIN
MAX
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
UNIT
3 V
2.9
2.9
IOH = 50
m
A
4.5 V
4.4
4.4
5.5 V
5.4
5.4
VOH
IOH = 4 mA
3 V
2.58
2.48
V
IOH = 24 mA
4.5 V
3.94
3.8
IOH = 24 mA
5.5 V
4.94
4.8
IOH = 75 mA
{
5.5 V
3.85
3 V
0.1
0.1
IOL = 50
m
A
4.5 V
0.1
0.1
5.5 V
0.1
0.1
VOL
IOL = 12 mA
3 V
0.36
0.44
V
IOL = 24 mA
4.5 V
0.36
0.44
IOL = 24 mA
5.5 V
0.36
0.44
IOL = 75 mA
{
5.5 V
1.65
IOZ
VO = VCC or GND
5.5 V
0.5
5
m
A
II
VI = VCC or GND
5.5 V
0.1
1
m
A
ICC
VI = VCC or GND, IO = 0
5.5 V
8
80
m
A
Ci
VI = VCC or GND
5 V
3.5
pF
Co
VO = VCC or GND
5 V
8.5
pF
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
74AC11286
9-BIT PARITY GENERATOR/CHECKER
WITH BUS DRIVER PARITY I/O PORTS
SCAS068A AUGUST 1988 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
24
switching characteristics over recommended operating free-air temperature range,
V
CC
= 3.3 V
0.3 V, (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25
C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
UNIT
tPLH
Any A thru I
PARITY I/O
2.6
10
11.7
2.6
13.1
ns
tPHL
Any A thru I
PARITY I/O
3.8
11.6
14.5
3.8
16.1
ns
tPLH
Any A thru I
PARITY ERROR
3
8.5
13.1
3
14.7
ns
tPHL
Any A thru I
PARITY ERROR
4
10.9
16
4
17.8
ns
tPLH
PARITY I/O
PARITY ERROR
2.2
5.9
7.6
2.2
8.4
ns
tPHL
PARITY I/O
PARITY ERROR
3.4
7.9
10.2
3.4
11.1
ns
tPZH
XMIT
PARITY I/O
1.8
4.9
6.4
1.8
7
ns
tPZL
XMIT
PARITY I/O
3.5
9.7
12.8
3.5
13.6
ns
tPHZ
XMIT
PARITY I/O
3.2
5.4
6.6
3.2
7
ns
tPLZ
XMIT
PARITY I/O
3.2
5.4
6.7
3.2
7.2
ns
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
0.5 V, (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25
C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
UNIT
tPLH
Any A thru I
PARITY I/O
2
5.5
8
2
9
ns
tPHL
Any A thru I
PARITY I/O
3.1
6.9
9.1
3.1
10.7
ns
tPLH
Any A thru I
PARITY ERROR
2.5
5.2
8.9
2.5
10
ns
tPHL
Any A thru I
PARITY ERROR
3.3
6.5
10.7
3.3
12
ns
tPLH
PARITY I/O
PARITY ERROR
1.9
3.9
5.6
1.9
6.2
ns
tPHL
PARITY I/O
PARITY ERROR
2.9
5
7.2
2.9
7.9
ns
tPZH
XMIT
PARITY I/O
1.4
3.3
4.9
1.4
5.3
ns
tPZL
XMIT
PARITY I/O
3
5.4
8.3
3
8.9
ns
tPHZ
XMIT
PARITY I/O
3.1
4.8
6.1
3.1
6.5
ns
tPLZ
XMIT
PARITY I/O
3
4.6
6
3
6.3
ns
operating characteristics, V
CC
= 5 V, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
C d
Power dissipation capacitance
Outputs enabled
CL = 50 pF
f = 1 MHz
53
pF
Cpd Power dissipation capacitance
Outputs disabled
CL = 50 pF, f = 1 MHz
46
pF
74AC11286
9-BIT PARITY GENERATOR/CHECKER
WITH BUS DRIVER PARITY I/O PORTS
SCAS068A AUGUST 1988 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
25
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
2
VCC
500
500
tPHL
tPLH
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2
VCC
(see Note C)
Output
Waveform 2
S1 at GND
(see Note C)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
50%
50%
50%
50%
[
VCC
VCC
0 V
50% VCC
50% VCC
VOH
VOL
0 V
50% VCC
20% VCC
50% VCC
80% VCC
[
0 V
VCC
GND
Open
Input
(see Note B)
Output
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2
VCC
GND
TEST
S1
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr = 3 ns, tf = 3 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
74AC11286
9-BIT PARITY GENERATOR/CHECKER
WITH BUS DRIVER PARITY I/O PORTS
SCAS068A AUGUST 1988 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
26
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Copyright
1998, Texas Instruments Incorporated
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